logic.vhd

5位的操作数X和Y输入后暂存在寄存器A和B中

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-- Company: 
-- Engineer:
--
-- Create Date:    21:51:02 12/09/08
-- Design Name:    
-- Module Name:    logic - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logic is
    port(
	      cin1,cin2: in std_logic_vector (4 downto 0);
	      cin3:  in std_logic_vector (1 downto 0);
	      clk,rst: in std_logic;
	      cout : out std_logic_vector (4 downto 0));
end logic;

architecture Behavioral of logic is

signal X,Y,Z1,Z2,Z3,Z4,cout1,cout2,cout3,cout4 :std_logic_vector (4 downto 0);
signal W :std_logic_vector (1 downto 0);
signal cin :std_logic;

begin
-------------------------------------
      D: process (clk,rst)
		begin
		       if(rst='1') then	 -- 一个带有一部复位端的D触发器的模型
				       X <= "00000";
						 Y<="00000";
						 W<="00";
						 cout1<="00000";
						 cout2<="00000";
						 cout3<="00000";
						 cout4<="00000"; -- 全部输出0	
  		       elsif (clk' event and clk='1') then --EVENT属性来检测时钟信号
						 X <= cin1;
						 Y <= cin2;
						 W <= cin3;
						 cout1 <= Z1;
						 cout2 <= Z2;
						 cout3 <= Z3;
						 cout4<=Z4;    --当上升沿出现时输入的值赋给输出
             end if;
 			end process D;

----------------------------------------		
		jiafa: process (X,Y)
		
			 VARIABLE c : std_logic_vector (4 downto 1);--  之前进位加法器的复用
			 begin
			 cin<='0';			         
	       c(1):=(X(0) and Y(0))or(X(0) and cin)or(Y(0) and cin);
	       c(2):=(X(1) and Y(1))or(X(1) and c(1))or(Y(1) and c(1));
	       c(3):=(X(2) and Y(2))or(X(2) and c(2))or(Y(2) and c(2));
	       c(4):=(X(3) and Y(3))or(X(3) and c(3))or(Y(3) and c(3));
			
	       cout1(0)<=X(0) xor Y(0) xor cin;
	       cout1(1)<=X(1) xor Y(1) xor c(1);
	       cout1(2)<=X(2) xor Y(2) xor c(2);
	       cout1(3)<=X(3) xor Y(3) xor c(3);
	       cout1(4)<=X(4) xor Y(4) xor c(4);
	    						 
		 end process jiafa;

-----------------------------------------------
		jianfa: process (X,Y) 
		
		
			 VARIABLE c : std_logic_vector (4 downto 1);
			 begin
			 cin<='1';
			 Y <= not Y;--  减法可以解释为取反加一				 			         		         
	       c(1):=(X(0) and Y(0))or(X(0) and cin)or(Y(0) and cin);
	       c(2):=(X(1) and Y(1))or(X(1) and c(1))or(Y(1) and c(1));
	       c(3):=(X(2) and Y(2))or(X(2) and c(2))or(Y(2) and c(2));
	       c(4):=(X(3) and Y(3))or(X(3) and c(3))or(X(3) and c(3));
			 
	       cout2(0)<=X(0) xor Y(0) xor cin;
	       cout2(1)<=X(1) xor Y(1) xor c(1);
	       cout2(2)<=X(2) xor Y(2) xor c(2);
	       cout2(3)<=X(3) xor Y(3) xor c(3);
	       cout2(4)<=X(4) xor Y(4) xor c(4);	
			 																							
		end process jianfa;
-----------------------------------------------

		chengfa: process (X,Y)
		begin
		
			   Z3<=(X and Y);
			   cout3<=Z3;
		
									
		end process chengfa;
---------------------------------------------------

		 yihuo: process (X,Y)
		 begin
		
				Z4<=(X xor Y);
				cout4<=Z4;
		 
		 end process yihuo;

----------------------------------------------------		
		 with W select
				cout <= cout1 when "00", 
					     cout2 when "01", 
						  cout3 when "10", 
						  cout4 when others; 



end Behavioral;