display.vhd

vhdl的铜须等

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
port(data : in  std_logic_vector(3 downto 0);
     seg_t: out std_logic_vector(6 downto 0));
end display;
architecture one of display is
signal temp:std_logic_vector(6 downto 0);
begin
  process(data)
    begin
      case data is
         when "0000"=>temp<="1111110";
         when "0001"=>temp<="0110000";
         when "0010"=>temp<="1101101";
         when "0011"=>temp<="1111001";
         when "0100"=>temp<="0110011";
         when "0101"=>temp<="1011011";
         when "0110"=>temp<="1011111";
         when "0111"=>temp<="1110000";
         when "1000"=>temp<="1111111";
         when "1001"=>temp<="1111011";
         when OTHERS=>temp<="1000111";
       end case;
   end process;
 seg_t<=temp;
end one;