ctr.tan.rpt

vhdl的铜须等

; N/A           ; None        ; -2.809 ns ; stop ; a         ; clk      ;
; N/A           ; None        ; -2.813 ns ; stop ; stax.sta2 ; clk      ;
; N/A           ; None        ; -2.814 ns ; stop ; stax.sta3 ; clk      ;
; N/A           ; None        ; -2.858 ns ; stop ; cl[1]     ; clk      ;
; N/A           ; None        ; -2.858 ns ; stop ; cl[0]     ; clk      ;
; N/A           ; None        ; -2.858 ns ; stop ; cl[2]     ; clk      ;
; N/A           ; None        ; -3.386 ns ; stop ; r1        ; clk      ;
; N/A           ; None        ; -3.386 ns ; stop ; g1        ; clk      ;
; N/A           ; None        ; -3.386 ns ; stop ; y1        ; clk      ;
; N/A           ; None        ; -3.386 ns ; stop ; g2        ; clk      ;
; N/A           ; None        ; -3.386 ns ; stop ; y2        ; clk      ;
; N/A           ; None        ; -3.510 ns ; stop ; stax.sta4 ; clk      ;
; N/A           ; None        ; -3.510 ns ; stop ; stax.sta1 ; clk      ;
; N/A           ; None        ; -3.788 ns ; stop ; ch[0]     ; clk      ;
; N/A           ; None        ; -3.788 ns ; stop ; ch[3]     ; clk      ;
; N/A           ; None        ; -3.788 ns ; stop ; ch[1]     ; clk      ;
; N/A           ; None        ; -3.950 ns ; stop ; ch[2]     ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat Nov 15 22:34:07 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ctr -c ctr --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 240.56 MHz between source register "cl[3]" and destination register "ch[2]" (period= 4.157 ns)
    Info: + Longest register to register delay is 3.982 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y22_N9; Fanout = 4; REG Node = 'cl[3]'
        Info: 2: + IC(0.994 ns) + CELL(0.183 ns) = 1.177 ns; Loc. = LC_X18_Y22_N5; Fanout = 3; COMB Node = 'Equal1~52'
        Info: 3: + IC(0.534 ns) + CELL(0.075 ns) = 1.786 ns; Loc. = LC_X18_Y22_N2; Fanout = 2; COMB Node = 'cl[0]~245'
        Info: 4: + IC(0.321 ns) + CELL(0.075 ns) = 2.182 ns; Loc. = LC_X18_Y22_N0; Fanout = 1; COMB Node = 'ch[0]~615'
        Info: 5: + IC(0.317 ns) + CELL(0.280 ns) = 2.779 ns; Loc. = LC_X18_Y22_N8; Fanout = 4; COMB Node = 'ch[0]~619'
        Info: 6: + IC(0.498 ns) + CELL(0.705 ns) = 3.982 ns; Loc. = LC_X19_Y22_N9; Fanout = 4; REG Node = 'ch[2]'
        Info: Total cell delay = 1.318 ns ( 33.10 % )
        Info: Total interconnect delay = 2.664 ns ( 66.90 % )
    Info: - Smallest clock skew is -0.009 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.943 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 18; CLK Node = 'clk'
            Info: 2: + IC(1.573 ns) + CELL(0.542 ns) = 2.943 ns; Loc. = LC_X19_Y22_N9; Fanout = 4; REG Node = 'ch[2]'
            Info: Total cell delay = 1.370 ns ( 46.55 % )
            Info: Total interconnect delay = 1.573 ns ( 53.45 % )
        Info: - Longest clock path from clock "clk" to source register is 2.952 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 18; CLK Node = 'clk'
            Info: 2: + IC(1.582 ns) + CELL(0.542 ns) = 2.952 ns; Loc. = LC_X14_Y22_N9; Fanout = 4; REG Node = 'cl[3]'
            Info: Total cell delay = 1.370 ns ( 46.41 % )
            Info: Total interconnect delay = 1.582 ns ( 53.59 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "ch[2]" (data pin = "stop", clock pin = "clk") is 4.060 ns
    Info: + Longest pin to register delay is 6.993 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G21; Fanout = 9; PIN Node = 'stop'
        Info: 2: + IC(3.981 ns) + CELL(0.366 ns) = 5.581 ns; Loc. = LC_X18_Y22_N7; Fanout = 1; COMB Node = 'ch[0]~617'
        Info: 3: + IC(0.134 ns) + CELL(0.075 ns) = 5.790 ns; Loc. = LC_X18_Y22_N8; Fanout = 4; COMB Node = 'ch[0]~619'
        Info: 4: + IC(0.498 ns) + CELL(0.705 ns) = 6.993 ns; Loc. = LC_X19_Y22_N9; Fanout = 4; REG Node = 'ch[2]'
        Info: Total cell delay = 2.380 ns ( 34.03 % )
        Info: Total interconnect delay = 4.613 ns ( 65.97 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.943 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(1.573 ns) + CELL(0.542 ns) = 2.943 ns; Loc. = LC_X19_Y22_N9; Fanout = 4; REG Node = 'ch[2]'
        Info: Total cell delay = 1.370 ns ( 46.55 % )
        Info: Total interconnect delay = 1.573 ns ( 53.45 % )
Info: tco from clock "clk" to destination pin "one[2]" through register "cl[2]" is 8.611 ns
    Info: + Longest clock path from clock "clk" to source register is 2.943 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(1.573 ns) + CELL(0.542 ns) = 2.943 ns; Loc. = LC_X19_Y22_N0; Fanout = 5; REG Node = 'cl[2]'
        Info: Total cell delay = 1.370 ns ( 46.55 % )
        Info: Total interconnect delay = 1.573 ns ( 53.45 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 5.512 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y22_N0; Fanout = 5; REG Node = 'cl[2]'
        Info: 2: + IC(3.108 ns) + CELL(2.404 ns) = 5.512 ns; Loc. = PIN_L16; Fanout = 0; PIN Node = 'one[2]'
        Info: Total cell delay = 2.404 ns ( 43.61 % )
        Info: Total interconnect delay = 3.108 ns ( 56.39 % )
Info: th for register "cl[3]" (data pin = "stop", clock pin = "clk") is -2.809 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.952 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(1.582 ns) + CELL(0.542 ns) = 2.952 ns; Loc. = LC_X14_Y22_N9; Fanout = 4; REG Node = 'cl[3]'
        Info: Total cell delay = 1.370 ns ( 46.41 % )
        Info: Total interconnect delay = 1.582 ns ( 53.59 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.861 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G21; Fanout = 9; PIN Node = 'stop'
        Info: 2: + IC(3.922 ns) + CELL(0.705 ns) = 5.861 ns; Loc. = LC_X14_Y22_N9; Fanout = 4; REG Node = 'cl[3]'
        Info: Total cell delay = 1.939 ns ( 33.08 % )
        Info: Total interconnect delay = 3.922 ns ( 66.92 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Sat Nov 15 22:34:08 2008
    Info: Elapsed time: 00:00:01