ctr.fit.smsg

vhdl的铜须等

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat Nov 15 22:33:52 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ctr -c ctr
Info: Automatically selected device EP1S10F484C5 for design ctr
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 59 of 59 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1S20F484C5 is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
    Info: Pin ~DATA0~ is reserved at location L8
Warning: No exact pin location assignment(s) for 16 pins of 16 total pins
    Info: Pin snr not assigned to an exact location on the device
    Info: Pin sng not assigned to an exact location on the device
    Info: Pin sny not assigned to an exact location on the device
    Info: Pin ewr not assigned to an exact location on the device
    Info: Pin ewg not assigned to an exact location on the device
    Info: Pin ewy not assigned to an exact location on the device
    Info: Pin one[0] not assigned to an exact location on the device
    Info: Pin one[1] not assigned to an exact location on the device
    Info: Pin one[2] not assigned to an exact location on the device
    Info: Pin one[3] not assigned to an exact location on the device
    Info: Pin ten[0] not assigned to an exact location on the device
    Info: Pin ten[1] not assigned to an exact location on the device
    Info: Pin ten[2] not assigned to an exact location on the device
    Info: Pin ten[3] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin stop not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN M20
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 15 (unused VREF, 3.30 VCCIO, 1 input, 14 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  28 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 3.571 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y22; Fanout = 4; REG Node = 'cl[3]'
    Info: 2: + IC(0.710 ns) + CELL(0.280 ns) = 0.990 ns; Loc. = LAB_X18_Y22; Fanout = 3; COMB Node = 'Equal1~52'
    Info: 3: + IC(0.393 ns) + CELL(0.075 ns) = 1.458 ns; Loc. = LAB_X18_Y22; Fanout = 2; COMB Node = 'Selector6~214'
    Info: 4: + IC(0.285 ns) + CELL(0.183 ns) = 1.926 ns; Loc. = LAB_X18_Y22; Fanout = 1; COMB Node = 'ch[0]~617'
    Info: 5: + IC(0.188 ns) + CELL(0.280 ns) = 2.394 ns; Loc. = LAB_X18_Y22; Fanout = 4; COMB Node = 'ch[0]~619'
    Info: 6: + IC(0.472 ns) + CELL(0.705 ns) = 3.571 ns; Loc. = LAB_X19_Y22; Fanout = 4; REG Node = 'ch[2]'
    Info: Total cell delay = 1.523 ns ( 42.65 % )
    Info: Total interconnect delay = 2.048 ns ( 57.35 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X10_Y21 to location X20_Y31
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 203 megabytes of memory during processing
    Info: Processing ended: Sat Nov 15 22:34:00 2008
    Info: Elapsed time: 00:00:08