ctr.tan.qmsg

vhdl的铜须等

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cl\[3\] register ch\[2\] 240.56 MHz 4.157 ns Internal " "Info: Clock \"clk\" has Internal fmax of 240.56 MHz between source register \"cl\[3\]\" and destination register \"ch\[2\]\" (period= 4.157 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.982 ns + Longest register register " "Info: + Longest register to register delay is 3.982 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cl\[3\] 1 REG LC_X14_Y22_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y22_N9; Fanout = 4; REG Node = 'cl\[3\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { cl[3] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.183 ns) 1.177 ns Equal1~52 2 COMB LC_X18_Y22_N5 3 " "Info: 2: + IC(0.994 ns) + CELL(0.183 ns) = 1.177 ns; Loc. = LC_X18_Y22_N5; Fanout = 3; COMB Node = 'Equal1~52'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.177 ns" { cl[3] Equal1~52 } "NODE_NAME" } } { "d:/peogram files/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/peogram files/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.075 ns) 1.786 ns cl\[0\]~245 3 COMB LC_X18_Y22_N2 2 " "Info: 3: + IC(0.534 ns) + CELL(0.075 ns) = 1.786 ns; Loc. = LC_X18_Y22_N2; Fanout = 2; COMB Node = 'cl\[0\]~245'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.609 ns" { Equal1~52 cl[0]~245 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(0.075 ns) 2.182 ns ch\[0\]~615 4 COMB LC_X18_Y22_N0 1 " "Info: 4: + IC(0.321 ns) + CELL(0.075 ns) = 2.182 ns; Loc. = LC_X18_Y22_N0; Fanout = 1; COMB Node = 'ch\[0\]~615'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.396 ns" { cl[0]~245 ch[0]~615 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.317 ns) + CELL(0.280 ns) 2.779 ns ch\[0\]~619 5 COMB LC_X18_Y22_N8 4 " "Info: 5: + IC(0.317 ns) + CELL(0.280 ns) = 2.779 ns; Loc. = LC_X18_Y22_N8; Fanout = 4; COMB Node = 'ch\[0\]~619'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.597 ns" { ch[0]~615 ch[0]~619 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.705 ns) 3.982 ns ch\[2\] 6 REG LC_X19_Y22_N9 4 " "Info: 6: + IC(0.498 ns) + CELL(0.705 ns) = 3.982 ns; Loc. = LC_X19_Y22_N9; Fanout = 4; REG Node = 'ch\[2\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.203 ns" { ch[0]~619 ch[2] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.318 ns ( 33.10 % ) " "Info: Total cell delay = 1.318 ns ( 33.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.664 ns ( 66.90 % ) " "Info: Total interconnect delay = 2.664 ns ( 66.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.982 ns" { cl[3] Equal1~52 cl[0]~245 ch[0]~615 ch[0]~619 ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "3.982 ns" { cl[3] Equal1~52 cl[0]~245 ch[0]~615 ch[0]~619 ch[2] } { 0.000ns 0.994ns 0.534ns 0.321ns 0.317ns 0.498ns } { 0.000ns 0.183ns 0.075ns 0.075ns 0.280ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.009 ns - Smallest " "Info: - Smallest clock skew is -0.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.943 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.943 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 18 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 18; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.573 ns) + CELL(0.542 ns) 2.943 ns ch\[2\] 2 REG LC_X19_Y22_N9 4 " "Info: 2: + IC(1.573 ns) + CELL(0.542 ns) = 2.943 ns; Loc. = LC_X19_Y22_N9; Fanout = 4; REG Node = 'ch\[2\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.115 ns" { clk ch[2] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.55 % ) " "Info: Total cell delay = 1.370 ns ( 46.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.573 ns ( 53.45 % ) " "Info: Total interconnect delay = 1.573 ns ( 53.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { clk ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { clk clk~out0 ch[2] } { 0.000ns 0.000ns 1.573ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.952 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 18 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 18; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.582 ns) + CELL(0.542 ns) 2.952 ns cl\[3\] 2 REG LC_X14_Y22_N9 4 " "Info: 2: + IC(1.582 ns) + CELL(0.542 ns) = 2.952 ns; Loc. = LC_X14_Y22_N9; Fanout = 4; REG Node = 'cl\[3\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.124 ns" { clk cl[3] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.41 % ) " "Info: Total cell delay = 1.370 ns ( 46.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.582 ns ( 53.59 % ) " "Info: Total interconnect delay = 1.582 ns ( 53.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.952 ns" { clk cl[3] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 cl[3] } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { clk ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { clk clk~out0 ch[2] } { 0.000ns 0.000ns 1.573ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.952 ns" { clk cl[3] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 cl[3] } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.982 ns" { cl[3] Equal1~52 cl[0]~245 ch[0]~615 ch[0]~619 ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "3.982 ns" { cl[3] Equal1~52 cl[0]~245 ch[0]~615 ch[0]~619 ch[2] } { 0.000ns 0.994ns 0.534ns 0.321ns 0.317ns 0.498ns } { 0.000ns 0.183ns 0.075ns 0.075ns 0.280ns 0.705ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { clk ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { clk clk~out0 ch[2] } { 0.000ns 0.000ns 1.573ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.952 ns" { clk cl[3] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 cl[3] } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ch\[2\] stop clk 4.060 ns register " "Info: tsu for register \"ch\[2\]\" (data pin = \"stop\", clock pin = \"clk\") is 4.060 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.993 ns + Longest pin register " "Info: + Longest pin to register delay is 6.993 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns stop 1 PIN PIN_G21 9 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G21; Fanout = 9; PIN Node = 'stop'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { stop } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.981 ns) + CELL(0.366 ns) 5.581 ns ch\[0\]~617 2 COMB LC_X18_Y22_N7 1 " "Info: 2: + IC(3.981 ns) + CELL(0.366 ns) = 5.581 ns; Loc. = LC_X18_Y22_N7; Fanout = 1; COMB Node = 'ch\[0\]~617'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.347 ns" { stop ch[0]~617 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 5.790 ns ch\[0\]~619 3 COMB LC_X18_Y22_N8 4 " "Info: 3: + IC(0.134 ns) + CELL(0.075 ns) = 5.790 ns; Loc. = LC_X18_Y22_N8; Fanout = 4; COMB Node = 'ch\[0\]~619'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.209 ns" { ch[0]~617 ch[0]~619 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.705 ns) 6.993 ns ch\[2\] 4 REG LC_X19_Y22_N9 4 " "Info: 4: + IC(0.498 ns) + CELL(0.705 ns) = 6.993 ns; Loc. = LC_X19_Y22_N9; Fanout = 4; REG Node = 'ch\[2\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.203 ns" { ch[0]~619 ch[2] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.380 ns ( 34.03 % ) " "Info: Total cell delay = 2.380 ns ( 34.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.613 ns ( 65.97 % ) " "Info: Total interconnect delay = 4.613 ns ( 65.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "6.993 ns" { stop ch[0]~617 ch[0]~619 ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "6.993 ns" { stop stop~out0 ch[0]~617 ch[0]~619 ch[2] } { 0.000ns 0.000ns 3.981ns 0.134ns 0.498ns } { 0.000ns 1.234ns 0.366ns 0.075ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.943 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.943 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 18 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 18; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.573 ns) + CELL(0.542 ns) 2.943 ns ch\[2\] 2 REG LC_X19_Y22_N9 4 " "Info: 2: + IC(1.573 ns) + CELL(0.542 ns) = 2.943 ns; Loc. = LC_X19_Y22_N9; Fanout = 4; REG Node = 'ch\[2\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.115 ns" { clk ch[2] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.55 % ) " "Info: Total cell delay = 1.370 ns ( 46.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.573 ns ( 53.45 % ) " "Info: Total interconnect delay = 1.573 ns ( 53.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { clk ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { clk clk~out0 ch[2] } { 0.000ns 0.000ns 1.573ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "6.993 ns" { stop ch[0]~617 ch[0]~619 ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "6.993 ns" { stop stop~out0 ch[0]~617 ch[0]~619 ch[2] } { 0.000ns 0.000ns 3.981ns 0.134ns 0.498ns } { 0.000ns 1.234ns 0.366ns 0.075ns 0.705ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { clk ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { clk clk~out0 ch[2] } { 0.000ns 0.000ns 1.573ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk one\[2\] cl\[2\] 8.611 ns register " "Info: tco from clock \"clk\" to destination pin \"one\[2\]\" through register \"cl\[2\]\" is 8.611 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.943 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.943 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 18 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 18; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.573 ns) + CELL(0.542 ns) 2.943 ns cl\[2\] 2 REG LC_X19_Y22_N0 5 " "Info: 2: + IC(1.573 ns) + CELL(0.542 ns) = 2.943 ns; Loc. = LC_X19_Y22_N0; Fanout = 5; REG Node = 'cl\[2\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.115 ns" { clk cl[2] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.55 % ) " "Info: Total cell delay = 1.370 ns ( 46.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.573 ns ( 53.45 % ) " "Info: Total interconnect delay = 1.573 ns ( 53.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { clk cl[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { clk clk~out0 cl[2] } { 0.000ns 0.000ns 1.573ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.512 ns + Longest register pin " "Info: + Longest register to pin delay is 5.512 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cl\[2\] 1 REG LC_X19_Y22_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y22_N0; Fanout = 5; REG Node = 'cl\[2\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { cl[2] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.108 ns) + CELL(2.404 ns) 5.512 ns one\[2\] 2 PIN PIN_L16 0 " "Info: 2: + IC(3.108 ns) + CELL(2.404 ns) = 5.512 ns; Loc. = PIN_L16; Fanout = 0; PIN Node = 'one\[2\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "5.512 ns" { cl[2] one[2] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 43.61 % ) " "Info: Total cell delay = 2.404 ns ( 43.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.108 ns ( 56.39 % ) " "Info: Total interconnect delay = 3.108 ns ( 56.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "5.512 ns" { cl[2] one[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "5.512 ns" { cl[2] one[2] } { 0.000ns 3.108ns } { 0.000ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { clk cl[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { clk clk~out0 cl[2] } { 0.000ns 0.000ns 1.573ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "5.512 ns" { cl[2] one[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "5.512 ns" { cl[2] one[2] } { 0.000ns 3.108ns } { 0.000ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "cl\[3\] stop clk -2.809 ns register " "Info: th for register \"cl\[3\]\" (data pin = \"stop\", clock pin = \"clk\") is -2.809 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.952 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 18 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 18; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.582 ns) + CELL(0.542 ns) 2.952 ns cl\[3\] 2 REG LC_X14_Y22_N9 4 " "Info: 2: + IC(1.582 ns) + CELL(0.542 ns) = 2.952 ns; Loc. = LC_X14_Y22_N9; Fanout = 4; REG Node = 'cl\[3\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.124 ns" { clk cl[3] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.41 % ) " "Info: Total cell delay = 1.370 ns ( 46.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.582 ns ( 53.59 % ) " "Info: Total interconnect delay = 1.582 ns ( 53.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.952 ns" { clk cl[3] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 cl[3] } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.861 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns stop 1 PIN PIN_G21 9 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G21; Fanout = 9; PIN Node = 'stop'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { stop } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.922 ns) + CELL(0.705 ns) 5.861 ns cl\[3\] 2 REG LC_X14_Y22_N9 4 " "Info: 2: + IC(3.922 ns) + CELL(0.705 ns) = 5.861 ns; Loc. = LC_X14_Y22_N9; Fanout = 4; REG Node = 'cl\[3\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.627 ns" { stop cl[3] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/vhd/state/ctr.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.939 ns ( 33.08 % ) " "Info: Total cell delay = 1.939 ns ( 33.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.922 ns ( 66.92 % ) " "Info: Total interconnect delay = 3.922 ns ( 66.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "5.861 ns" { stop cl[3] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "5.861 ns" { stop stop~out0 cl[3] } { 0.000ns 0.000ns 3.922ns } { 0.000ns 1.234ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.952 ns" { clk cl[3] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.952 ns" { clk clk~out0 cl[3] } { 0.000ns 0.000ns 1.582ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "5.861 ns" { stop cl[3] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "5.861 ns" { stop stop~out0 cl[3] } { 0.000ns 0.000ns 3.922ns } { 0.000ns 1.234ns 0.705ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}