ctr.vhd

vhdl的铜须等

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ctr is
port(stop,clk:in  std_logic;
     snr,sng,sny:out std_logic;
     ewr,ewg,ewy:out std_logic;
     one,ten: out std_logic_vector(3 downto 0));
end ctr;
architecture one of ctr is
type states is(sta1,sta2,sta3,sta4);
signal r1,g1,y1,r2,y2,g2:std_logic;
signal ch,cl:std_logic_vector(3 downto 0);
begin
  process(clk)
  variable a: std_logic;
  variable stax: states;
--  variable ch,cl:std_logic_vector(3 downto 0);
  begin
    if(clk 'event and clk='1')then
       case stax is
         when sta1=>if(stop='0')then
                      if(a='0')then
                        ch<="0011";
                        cl<="1001";
                         a:='1';
                        r1<='0';
                        g1<='1';
                        y1<='0';
                        r2<='1';
                        g2<='0';
                        y2<='0';
                      else
                        if(ch=0 and cl=1)then
                          stax:=sta2;
                          a:='0';
                          ch<="0000";
                          cl<="0000";
                        elsif(cl=0)then
                          cl<="1001";
                          ch<=ch-1;
                        else
                          cl<=cl-1;
                        end if;
                      end if;
                  end if;
      when sta2=>if(stop='0')then
                    if(a='0')then
                      cl<="0100";
                       a:='1';
                      r1<='0';
                      g1<='0';
                      y1<='1';
                      r2<='1';
                      g2<='0';
                      y2<='0';                  
                    else
                      if(cl=1)then
                         stax:=sta3;
                         a:='0';
                         ch<="0000";
                         cl<="0000";
                      else
                         cl<=cl-1;
                     end if;
                   end if;
                 end if;
      when sta3=>if(stop='0')then
                    if(a='0')then
                      ch<="0011";
                      cl<="1001";
                       a:='1';
                      r1<='1';
                      g1<='0';
                      y1<='0';
                      r2<='0';
                      g2<='1';
                      y2<='0';
                   else
                     if(ch=0 and cl=1)then
                       stax:=sta4;
                       a:='0';
                       ch<="0000";
                       cl<="0000";
                     elsif(cl=0)then
                       cl<="1001";
                       ch<=ch-1;
                     else
                       cl<=cl-1;
                     end if;
                   end if;
                 end if;
       when sta4=>if(stop='0')then
                    if(a='0')then
                      cl<="0100";
                       a:='1';
                      r1<='1';
                      g1<='0';
                      y1<='0';
                      r2<='0';
                      g2<='0';
                      y2<='1';
                     elsif(ch=0 and cl=1)then
                       stax:=sta1;
                       a:='0';
                       ch<="0000";
                       cl<="0000";
                     else
                       cl<=cl-1;
                     end if;
                   end if;
      end case;
end if;
end process;
one<=cl;
ten<=ch;
snr<=r1 ;
sng<=g1 ;
sny<=y1 ;
ewr<=r2 ;
ewg<=g2 ;
ewy<=y2 ;
end one;