saomiao.tan.qmsg

vhdl的铜须等

{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[2\] cnt\[0\] 7.354 ns register " "Info: tco from clock \"clk\" to destination pin \"data\[2\]\" through register \"cnt\[0\]\" is 7.354 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.720 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns clk 1 CLK PIN_U20 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.944 ns) + CELL(0.542 ns) 2.720 ns cnt\[0\] 2 REG LC_X7_Y1_N9 7 " "Info: 2: + IC(0.944 ns) + CELL(0.542 ns) = 2.720 ns; Loc. = LC_X7_Y1_N9; Fanout = 7; REG Node = 'cnt\[0\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.486 ns" { clk cnt[0] } "NODE_NAME" } } { "saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 65.29 % ) " "Info: Total cell delay = 1.776 ns ( 65.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.944 ns ( 34.71 % ) " "Info: Total interconnect delay = 0.944 ns ( 34.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.720 ns" { clk cnt[0] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.720 ns" { clk clk~out0 cnt[0] } { 0.000ns 0.000ns 0.944ns } { 0.000ns 1.234ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.478 ns + Longest register pin " "Info: + Longest register to pin delay is 4.478 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LC_X7_Y1_N9 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N9; Fanout = 7; REG Node = 'cnt\[0\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.183 ns) 0.746 ns Mux5~14 2 COMB LC_X7_Y1_N2 1 " "Info: 2: + IC(0.563 ns) + CELL(0.183 ns) = 0.746 ns; Loc. = LC_X7_Y1_N2; Fanout = 1; COMB Node = 'Mux5~14'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.746 ns" { cnt[0] Mux5~14 } "NODE_NAME" } } { "saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.328 ns) + CELL(2.404 ns) 4.478 ns data\[2\] 3 PIN PIN_N13 0 " "Info: 3: + IC(1.328 ns) + CELL(2.404 ns) = 4.478 ns; Loc. = PIN_N13; Fanout = 0; PIN Node = 'data\[2\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.732 ns" { Mux5~14 data[2] } "NODE_NAME" } } { "saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.587 ns ( 57.77 % ) " "Info: Total cell delay = 2.587 ns ( 57.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.891 ns ( 42.23 % ) " "Info: Total interconnect delay = 1.891 ns ( 42.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.478 ns" { cnt[0] Mux5~14 data[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "4.478 ns" { cnt[0] Mux5~14 data[2] } { 0.000ns 0.563ns 1.328ns } { 0.000ns 0.183ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.720 ns" { clk cnt[0] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.720 ns" { clk clk~out0 cnt[0] } { 0.000ns 0.000ns 0.944ns } { 0.000ns 1.234ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.478 ns" { cnt[0] Mux5~14 data[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "4.478 ns" { cnt[0] Mux5~14 data[2] } { 0.000ns 0.563ns 1.328ns } { 0.000ns 0.183ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "one\[3\] data\[3\] 9.092 ns Longest " "Info: Longest tpd from source pin \"one\[3\]\" to destination pin \"data\[3\]\" is 9.092 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns one\[3\] 1 PIN PIN_Y18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y18; Fanout = 1; PIN Node = 'one\[3\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { one[3] } "NODE_NAME" } } { "saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.902 ns) + CELL(0.366 ns) 5.355 ns Mux6~14 2 COMB LC_X7_Y1_N8 1 " "Info: 2: + IC(3.902 ns) + CELL(0.366 ns) = 5.355 ns; Loc. = LC_X7_Y1_N8; Fanout = 1; COMB Node = 'Mux6~14'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.268 ns" { one[3] Mux6~14 } "NODE_NAME" } } { "saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.333 ns) + CELL(2.404 ns) 9.092 ns data\[3\] 3 PIN PIN_W17 0 " "Info: 3: + IC(1.333 ns) + CELL(2.404 ns) = 9.092 ns; Loc. = PIN_W17; Fanout = 0; PIN Node = 'data\[3\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.737 ns" { Mux6~14 data[3] } "NODE_NAME" } } { "saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.857 ns ( 42.42 % ) " "Info: Total cell delay = 3.857 ns ( 42.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.235 ns ( 57.58 % ) " "Info: Total interconnect delay = 5.235 ns ( 57.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "9.092 ns" { one[3] Mux6~14 data[3] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "9.092 ns" { one[3] one[3]~out0 Mux6~14 data[3] } { 0.000ns 0.000ns 3.902ns 1.333ns } { 0.000ns 1.087ns 0.366ns 2.404ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "99 " "Info: Allocated 99 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 14 22:58:27 2008 " "Info: Processing ended: Fri Nov 14 22:58:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}