saomiao.map.rpt

vhdl的铜须等

+-------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                      ;
+----------------------------------+-----------------+-----------------+--------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path         ;
+----------------------------------+-----------------+-----------------+--------------------------------------+
; saomiao.vhd                      ; yes             ; User VHDL File  ; E:/vhd/jiaotongdeng/scan/saomiao.vhd ;
+----------------------------------+-----------------+-----------------+--------------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+---------------------------------------------+--------+
; Resource                                    ; Usage  ;
+---------------------------------------------+--------+
; Total logic elements                        ; 6      ;
;     -- Combinational with no register       ; 5      ;
;     -- Register only                        ; 0      ;
;     -- Combinational with a register        ; 1      ;
;                                             ;        ;
; Logic element usage by number of LUT inputs ;        ;
;     -- 4 input functions                    ; 0      ;
;     -- 3 input functions                    ; 4      ;
;     -- 2 input functions                    ; 0      ;
;     -- 1 input functions                    ; 2      ;
;     -- 0 input functions                    ; 0      ;
;                                             ;        ;
; Logic elements by mode                      ;        ;
;     -- normal mode                          ; 6      ;
;     -- arithmetic mode                      ; 0      ;
;     -- qfbk mode                            ; 0      ;
;     -- register cascade mode                ; 0      ;
;     -- synchronous clear/load mode          ; 0      ;
;     -- asynchronous clear/load mode         ; 0      ;
;                                             ;        ;
; Total registers                             ; 1      ;
; I/O pins                                    ; 0      ;
; Maximum fan-out node                        ; cnt[0] ;
; Maximum fan-out                             ; 7      ;
; Total fan-out                               ; 21     ;
; Average fan-out                             ; 1.00   ;
+---------------------------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                     ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |saomiao                   ; 6 (6)       ; 1            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 1 (1)            ; 0 (0)           ; 0 (0)      ; |saomiao            ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; cnt[1]                                ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 1 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Nov 14 22:58:06 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off saomiao -c saomiao
Info: Found 2 design units, including 1 entities, in source file saomiao.vhd
    Info: Found design unit 1: saomiao-one
    Info: Found entity 1: saomiao
Info: Elaborating entity "saomiao" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at saomiao.vhd(31): signal "d" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at saomiao.vhd(24): inferring latch(es) for signal or variable "d", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at saomiao.vhd(24): inferring latch(es) for signal or variable "adr", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "adr[0]"
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "adr[1]"
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "d[0]"
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "d[1]"
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "d[2]"
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "d[3]"
Warning: Reduced register "cnt[1]" with stuck data_in port to stuck value GND
Warning: LATCH primitive "d[0]" is permanently enabled
Warning: LATCH primitive "d[1]" is permanently enabled
Warning: LATCH primitive "d[2]" is permanently enabled
Warning: LATCH primitive "d[3]" is permanently enabled
Warning: LATCH primitive "adr[0]$latch" is permanently enabled
Warning: LATCH primitive "adr[1]$latch" is permanently enabled
Info: Implemented 21 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 6 output pins
    Info: Implemented 6 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Allocated 139 megabytes of memory during processing
    Info: Processing ended: Fri Nov 14 22:58:08 2008
    Info: Elapsed time: 00:00:02