traffic_lights.fit.qmsg

vhdl的铜须等

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.015 ns register register " "Info: Estimated most critical path is register to register delay of 4.015 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns saomiao:u2\|cnt\[0\] 1 REG LAB_X30_Y23 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X30_Y23; Fanout = 11; REG Node = 'saomiao:u2\|cnt\[0\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { saomiao:u2|cnt[0] } "NODE_NAME" } } { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.920 ns) + CELL(0.443 ns) 2.363 ns fenpin:u0\|Add0~136 2 COMB LAB_X2_Y15 2 " "Info: 2: + IC(1.920 ns) + CELL(0.443 ns) = 2.363 ns; Loc. = LAB_X2_Y15; Fanout = 2; COMB Node = 'fenpin:u0\|Add0~136'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { saomiao:u2|cnt[0] fenpin:u0|Add0~136 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 2.421 ns fenpin:u0\|Add0~138 3 COMB LAB_X2_Y15 2 " "Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 2.421 ns; Loc. = LAB_X2_Y15; Fanout = 2; COMB Node = 'fenpin:u0\|Add0~138'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { fenpin:u0|Add0~136 fenpin:u0|Add0~138 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 2.479 ns fenpin:u0\|Add0~140 4 COMB LAB_X2_Y15 2 " "Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 2.479 ns; Loc. = LAB_X2_Y15; Fanout = 2; COMB Node = 'fenpin:u0\|Add0~140'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { fenpin:u0|Add0~138 fenpin:u0|Add0~140 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 2.537 ns fenpin:u0\|Add0~144 5 COMB LAB_X2_Y15 2 " "Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 2.537 ns; Loc. = LAB_X2_Y15; Fanout = 2; COMB Node = 'fenpin:u0\|Add0~144'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { fenpin:u0|Add0~140 fenpin:u0|Add0~144 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.214 ns) 2.751 ns fenpin:u0\|Add0~146 6 COMB LAB_X2_Y15 3 " "Info: 6: + IC(0.000 ns) + CELL(0.214 ns) = 2.751 ns; Loc. = LAB_X2_Y15; Fanout = 3; COMB Node = 'fenpin:u0\|Add0~146'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.214 ns" { fenpin:u0|Add0~144 fenpin:u0|Add0~146 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.469 ns) 3.220 ns fenpin:u0\|Add0~147 7 COMB LAB_X2_Y15 1 " "Info: 7: + IC(0.000 ns) + CELL(0.469 ns) = 3.220 ns; Loc. = LAB_X2_Y15; Fanout = 1; COMB Node = 'fenpin:u0\|Add0~147'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.469 ns" { fenpin:u0|Add0~146 fenpin:u0|Add0~147 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.256 ns) + CELL(0.539 ns) 4.015 ns fenpin:u0\|cnt\[6\] 8 REG LAB_X1_Y15 4 " "Info: 8: + IC(0.256 ns) + CELL(0.539 ns) = 4.015 ns; Loc. = LAB_X1_Y15; Fanout = 4; REG Node = 'fenpin:u0\|cnt\[6\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.795 ns" { fenpin:u0|Add0~147 fenpin:u0|cnt[6] } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.839 ns ( 45.80 % ) " "Info: Total cell delay = 1.839 ns ( 45.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.176 ns ( 54.20 % ) " "Info: Total interconnect delay = 2.176 ns ( 54.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.015 ns" { saomiao:u2|cnt[0] fenpin:u0|Add0~136 fenpin:u0|Add0~138 fenpin:u0|Add0~140 fenpin:u0|Add0~144 fenpin:u0|Add0~146 fenpin:u0|Add0~147 fenpin:u0|cnt[6] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X21_Y21 X31_Y31 " "Info: The peak interconnect region extends from location X21_Y21 to location X31_Y31" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "203 " "Info: Allocated 203 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 15 22:03:22 2008 " "Info: Processing ended: Sat Nov 15 22:03:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.fit.smsg " "Info: Generated suppressed messages file E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}