traffic_lights.map.qmsg

vhdl的铜须等

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dplay dplay:u4 " "Info: Elaborating entity \"dplay\" for hierarchy \"dplay:u4\"" {  } { { "traffic_lights.vhd" "u4" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 58 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk dplay.vhd(25) " "Warning (10492): VHDL Process Statement warning at dplay.vhd(25): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../xianshi/dplay.vhd" "" { Text "E:/vhd/jiaotongdeng/xianshi/dplay.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk dplay.vhd(26) " "Warning (10492): VHDL Process Statement warning at dplay.vhd(26): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../xianshi/dplay.vhd" "" { Text "E:/vhd/jiaotongdeng/xianshi/dplay.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk dplay.vhd(27) " "Warning (10492): VHDL Process Statement warning at dplay.vhd(27): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../xianshi/dplay.vhd" "" { Text "E:/vhd/jiaotongdeng/xianshi/dplay.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk dplay.vhd(28) " "Warning (10492): VHDL Process Statement warning at dplay.vhd(28): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../xianshi/dplay.vhd" "" { Text "E:/vhd/jiaotongdeng/xianshi/dplay.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk dplay.vhd(29) " "Warning (10492): VHDL Process Statement warning at dplay.vhd(29): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../xianshi/dplay.vhd" "" { Text "E:/vhd/jiaotongdeng/xianshi/dplay.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk dplay.vhd(30) " "Warning (10492): VHDL Process Statement warning at dplay.vhd(30): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../xianshi/dplay.vhd" "" { Text "E:/vhd/jiaotongdeng/xianshi/dplay.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk dplay.vhd(31) " "Warning (10492): VHDL Process Statement warning at dplay.vhd(31): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../xianshi/dplay.vhd" "" { Text "E:/vhd/jiaotongdeng/xianshi/dplay.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "ctr:u1\|r2 ctr:u1\|r1 " "Info: Duplicate register \"ctr:u1\|r2\" merged to single register \"ctr:u1\|r1\", power-up level changed" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|traffic_lights\|ctr:u1\|stax 4 " "Info: State machine \"\|traffic_lights\|ctr:u1\|stax\" contains 4 states" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 17 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|traffic_lights\|ctr:u1\|stax " "Info: Selected Auto state machine encoding method for state machine \"\|traffic_lights\|ctr:u1\|stax\"" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 17 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|traffic_lights\|ctr:u1\|stax " "Info: Encoding result for state machine \"\|traffic_lights\|ctr:u1\|stax\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ctr:u1\|stax.sta4 " "Info: Encoded state bit \"ctr:u1\|stax.sta4\"" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ctr:u1\|stax.sta3 " "Info: Encoded state bit \"ctr:u1\|stax.sta3\"" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ctr:u1\|stax.sta2 " "Info: Encoded state bit \"ctr:u1\|stax.sta2\"" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ctr:u1\|stax.sta1 " "Info: Encoded state bit \"ctr:u1\|stax.sta1\"" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic_lights\|ctr:u1\|stax.sta1 0000 " "Info: State \"\|traffic_lights\|ctr:u1\|stax.sta1\" uses code string \"0000\"" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic_lights\|ctr:u1\|stax.sta2 0011 " "Info: State \"\|traffic_lights\|ctr:u1\|stax.sta2\" uses code string \"0011\"" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic_lights\|ctr:u1\|stax.sta3 0101 " "Info: State \"\|traffic_lights\|ctr:u1\|stax.sta3\" uses code string \"0101\"" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic_lights\|ctr:u1\|stax.sta4 1001 " "Info: State \"\|traffic_lights\|ctr:u1\|stax.sta4\" uses code string \"1001\"" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 17 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "fenpin:u0\|cnt\[0\] saomiao:u2\|cnt\[0\] " "Info: Duplicate register \"fenpin:u0\|cnt\[0\]\" merged to single register \"saomiao:u2\|cnt\[0\]\"" {  } { { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "saomiao:u2\|cnt\[1\] data_in GND " "Warning: Reduced register \"saomiao:u2\|cnt\[1\]\" with stuck data_in port to stuck value GND" {  } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "saomiao:u2\|adr\[0\] " "Warning: LATCH primitive \"saomiao:u2\|adr\[0\]\" is permanently enabled" {  } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "saomiao:u2\|adr\[1\] " "Warning: LATCH primitive \"saomiao:u2\|adr\[1\]\" is permanently enabled" {  } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "saomiao:u2\|d\[0\] " "Warning: LATCH primitive \"saomiao:u2\|d\[0\]\" is permanently enabled" {  } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "saomiao:u2\|d\[1\] " "Warning: LATCH primitive \"saomiao:u2\|d\[1\]\" is permanently enabled" {  } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "saomiao:u2\|d\[2\] " "Warning: LATCH primitive \"saomiao:u2\|d\[2\]\" is permanently enabled" {  } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "saomiao:u2\|d\[3\] " "Warning: LATCH primitive \"saomiao:u2\|d\[3\]\" is permanently enabled" {  } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "105 " "Info: Implemented 105 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "88 " "Info: Implemented 88 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 15 22:03:11 2008 " "Info: Processing ended: Sat Nov 15 22:03:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}