📄 traffic_lights.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 15 22:03:08 2008 " "Info: Processing started: Sat Nov 15 22:03:08 2008" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off traffic_lights -c traffic_lights " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic_lights -c traffic_lights" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../xianshi/dplay.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../xianshi/dplay.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dplay-one " "Info: Found design unit 1: dplay-one" { } { { "../xianshi/dplay.vhd" "" { Text "E:/vhd/jiaotongdeng/xianshi/dplay.vhd" 14 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dplay " "Info: Found entity 1: dplay" { } { { "../xianshi/dplay.vhd" "" { Text "E:/vhd/jiaotongdeng/xianshi/dplay.vhd" 4 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../state/Vhdl1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../state/Vhdl1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ctr-one " "Info: Found design unit 1: ctr-one" { } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 10 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ctr " "Info: Found entity 1: ctr" { } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 4 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../scan/saomiao.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../scan/saomiao.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 saomiao-one " "Info: Found design unit 1: saomiao-one" { } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 10 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 saomiao " "Info: Found entity 1: saomiao" { } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 4 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../fenpin/fenpin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../fenpin/fenpin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin-one " "Info: Found design unit 1: fenpin-one" { } { { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 8 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" { } { { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 4 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../display/display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../display/display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-one " "Info: Found design unit 1: display-one" { } { { "../display/display.vhd" "" { Text "E:/vhd/jiaotongdeng/display/display.vhd" 8 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" { } { { "../display/display.vhd" "" { Text "E:/vhd/jiaotongdeng/display/display.vhd" 4 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic_lights.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file traffic_lights.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 traffic_lights-rtl " "Info: Found design unit 1: traffic_lights-rtl" { } { { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 12 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 traffic_lights " "Info: Found entity 1: traffic_lights" { } { { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 4 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "traffic_lights " "Info: Elaborating entity \"traffic_lights\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin fenpin:u0 " "Info: Elaborating entity \"fenpin\" for hierarchy \"fenpin:u0\"" { } { { "traffic_lights.vhd" "u0" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 54 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ctr ctr:u1 " "Info: Elaborating entity \"ctr\" for hierarchy \"ctr:u1\"" { } { { "traffic_lights.vhd" "u1" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 55 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "saomiao saomiao:u2 " "Info: Elaborating entity \"saomiao\" for hierarchy \"saomiao:u2\"" { } { { "traffic_lights.vhd" "u2" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 56 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d saomiao.vhd(31) " "Warning (10492): VHDL Process Statement warning at saomiao.vhd(31): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 31 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "d saomiao.vhd(24) " "Warning (10631): VHDL Process Statement warning at saomiao.vhd(24): inferring latch(es) for signal or variable \"d\", which holds its previous value in one or more paths through the process" { } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "adr saomiao.vhd(24) " "Warning (10631): VHDL Process Statement warning at saomiao.vhd(24): inferring latch(es) for signal or variable \"adr\", which holds its previous value in one or more paths through the process" { } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "adr\[0\] saomiao.vhd(24) " "Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for \"adr\[0\]\"" { } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "adr\[1\] saomiao.vhd(24) " "Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for \"adr\[1\]\"" { } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "d\[0\] saomiao.vhd(24) " "Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for \"d\[0\]\"" { } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "d\[1\] saomiao.vhd(24) " "Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for \"d\[1\]\"" { } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "d\[2\] saomiao.vhd(24) " "Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for \"d\[2\]\"" { } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "d\[3\] saomiao.vhd(24) " "Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for \"d\[3\]\"" { } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 24 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display display:u3 " "Info: Elaborating entity \"display\" for hierarchy \"display:u3\"" { } { { "traffic_lights.vhd" "u3" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 57 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
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