traffic_lights.tan.qmsg

vhdl的铜须等

{ "Info" "ITDB_FULL_TPD_RESULT" "stop sng 9.844 ns Longest " "Info: Longest tpd from source pin \"stop\" to destination pin \"sng\" is 9.844 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns stop 1 PIN PIN_J8 21 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J8; Fanout = 21; PIN Node = 'stop'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { stop } "NODE_NAME" } } { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.232 ns) + CELL(0.366 ns) 5.685 ns dplay:u4\|sng~11 2 COMB LC_X30_Y24_N9 1 " "Info: 2: + IC(4.232 ns) + CELL(0.366 ns) = 5.685 ns; Loc. = LC_X30_Y24_N9; Fanout = 1; COMB Node = 'dplay:u4\|sng~11'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.598 ns" { stop dplay:u4|sng~11 } "NODE_NAME" } } { "../xianshi/dplay.vhd" "" { Text "E:/vhd/jiaotongdeng/xianshi/dplay.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.472 ns) + CELL(2.687 ns) 9.844 ns sng 3 PIN PIN_B12 0 " "Info: 3: + IC(1.472 ns) + CELL(2.687 ns) = 9.844 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'sng'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.159 ns" { dplay:u4|sng~11 sng } "NODE_NAME" } } { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.140 ns ( 42.06 % ) " "Info: Total cell delay = 4.140 ns ( 42.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.704 ns ( 57.94 % ) " "Info: Total interconnect delay = 5.704 ns ( 57.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "9.844 ns" { stop dplay:u4|sng~11 sng } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "9.844 ns" { stop stop~out0 dplay:u4|sng~11 sng } { 0.000ns 0.000ns 4.232ns 1.472ns } { 0.000ns 1.087ns 0.366ns 2.687ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ctr:u1\|cl\[1\] stop clk 1.301 ns register " "Info: th for register \"ctr:u1\|cl\[1\]\" (data pin = \"stop\", clock pin = \"clk\") is 1.301 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.883 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.883 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 10 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.682 ns) + CELL(0.698 ns) 3.208 ns fenpin:u0\|q 2 REG LC_X1_Y15_N7 26 " "Info: 2: + IC(1.682 ns) + CELL(0.698 ns) = 3.208 ns; Loc. = LC_X1_Y15_N7; Fanout = 26; REG Node = 'fenpin:u0\|q'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.380 ns" { clk fenpin:u0|q } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.133 ns) + CELL(0.542 ns) 6.883 ns ctr:u1\|cl\[1\] 3 REG LC_X33_Y25_N1 6 " "Info: 3: + IC(3.133 ns) + CELL(0.542 ns) = 6.883 ns; Loc. = LC_X33_Y25_N1; Fanout = 6; REG Node = 'ctr:u1\|cl\[1\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.675 ns" { fenpin:u0|q ctr:u1|cl[1] } "NODE_NAME" } } { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns ( 30.05 % ) " "Info: Total cell delay = 2.068 ns ( 30.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.815 ns ( 69.95 % ) " "Info: Total interconnect delay = 4.815 ns ( 69.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "6.883 ns" { clk fenpin:u0|q ctr:u1|cl[1] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "6.883 ns" { clk clk~out0 fenpin:u0|q ctr:u1|cl[1] } { 0.000ns 0.000ns 1.682ns 3.133ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.682 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns stop 1 PIN PIN_J8 21 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J8; Fanout = 21; PIN Node = 'stop'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { stop } "NODE_NAME" } } { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.890 ns) + CELL(0.705 ns) 5.682 ns ctr:u1\|cl\[1\] 2 REG LC_X33_Y25_N1 6 " "Info: 2: + IC(3.890 ns) + CELL(0.705 ns) = 5.682 ns; Loc. = LC_X33_Y25_N1; Fanout = 6; REG Node = 'ctr:u1\|cl\[1\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.595 ns" { stop ctr:u1|cl[1] } "NODE_NAME" } } { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.792 ns ( 31.54 % ) " "Info: Total cell delay = 1.792 ns ( 31.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.890 ns ( 68.46 % ) " "Info: Total interconnect delay = 3.890 ns ( 68.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "5.682 ns" { stop ctr:u1|cl[1] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "5.682 ns" { stop stop~out0 ctr:u1|cl[1] } { 0.000ns 0.000ns 3.890ns } { 0.000ns 1.087ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "6.883 ns" { clk fenpin:u0|q ctr:u1|cl[1] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "6.883 ns" { clk clk~out0 fenpin:u0|q ctr:u1|cl[1] } { 0.000ns 0.000ns 1.682ns 3.133ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "5.682 ns" { stop ctr:u1|cl[1] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "5.682 ns" { stop stop~out0 ctr:u1|cl[1] } { 0.000ns 0.000ns 3.890ns } { 0.000ns 1.087ns 0.705ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 15 22:03:30 2008 " "Info: Processing ended: Sat Nov 15 22:03:30 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}