traffic_lights.tan.qmsg

vhdl的铜须等

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fenpin:u0\|q " "Info: Detected ripple clock \"fenpin:u0\|q\" as buffer" {  } { { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } } { "d:/peogram files/alter/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/peogram files/alter/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpin:u0\|q" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register saomiao:u2\|cnt\[0\] register fenpin:u0\|cnt\[7\] 244.38 MHz 4.092 ns Internal " "Info: Clock \"clk\" has Internal fmax of 244.38 MHz between source register \"saomiao:u2\|cnt\[0\]\" and destination register \"fenpin:u0\|cnt\[7\]\" (period= 4.092 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.075 ns + Longest register register " "Info: + Longest register to register delay is 4.075 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns saomiao:u2\|cnt\[0\] 1 REG LC_X30_Y23_N5 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y23_N5; Fanout = 11; REG Node = 'saomiao:u2\|cnt\[0\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { saomiao:u2|cnt[0] } "NODE_NAME" } } { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.030 ns) + CELL(0.451 ns) 2.481 ns fenpin:u0\|Add0~136COUT1 2 COMB LC_X2_Y15_N0 2 " "Info: 2: + IC(2.030 ns) + CELL(0.451 ns) = 2.481 ns; Loc. = LC_X2_Y15_N0; Fanout = 2; COMB Node = 'fenpin:u0\|Add0~136COUT1'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { saomiao:u2|cnt[0] fenpin:u0|Add0~136COUT1 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 2.541 ns fenpin:u0\|Add0~138COUT1 3 COMB LC_X2_Y15_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 2.541 ns; Loc. = LC_X2_Y15_N1; Fanout = 2; COMB Node = 'fenpin:u0\|Add0~138COUT1'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { fenpin:u0|Add0~136COUT1 fenpin:u0|Add0~138COUT1 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 2.601 ns fenpin:u0\|Add0~140COUT1 4 COMB LC_X2_Y15_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 2.601 ns; Loc. = LC_X2_Y15_N2; Fanout = 2; COMB Node = 'fenpin:u0\|Add0~140COUT1'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { fenpin:u0|Add0~138COUT1 fenpin:u0|Add0~140COUT1 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 2.661 ns fenpin:u0\|Add0~144COUT1 5 COMB LC_X2_Y15_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 2.661 ns; Loc. = LC_X2_Y15_N3; Fanout = 2; COMB Node = 'fenpin:u0\|Add0~144COUT1'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { fenpin:u0|Add0~140COUT1 fenpin:u0|Add0~144COUT1 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.118 ns) 2.779 ns fenpin:u0\|Add0~146 6 COMB LC_X2_Y15_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.118 ns) = 2.779 ns; Loc. = LC_X2_Y15_N4; Fanout = 3; COMB Node = 'fenpin:u0\|Add0~146'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { fenpin:u0|Add0~144COUT1 fenpin:u0|Add0~146 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 3.228 ns fenpin:u0\|Add0~149 7 COMB LC_X2_Y15_N6 1 " "Info: 7: + IC(0.000 ns) + CELL(0.449 ns) = 3.228 ns; Loc. = LC_X2_Y15_N6; Fanout = 1; COMB Node = 'fenpin:u0\|Add0~149'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.449 ns" { fenpin:u0|Add0~146 fenpin:u0|Add0~149 } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.528 ns) + CELL(0.319 ns) 4.075 ns fenpin:u0\|cnt\[7\] 8 REG LC_X1_Y15_N5 4 " "Info: 8: + IC(0.528 ns) + CELL(0.319 ns) = 4.075 ns; Loc. = LC_X1_Y15_N5; Fanout = 4; REG Node = 'fenpin:u0\|cnt\[7\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.847 ns" { fenpin:u0|Add0~149 fenpin:u0|cnt[7] } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.517 ns ( 37.23 % ) " "Info: Total cell delay = 1.517 ns ( 37.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.558 ns ( 62.77 % ) " "Info: Total interconnect delay = 2.558 ns ( 62.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.075 ns" { saomiao:u2|cnt[0] fenpin:u0|Add0~136COUT1 fenpin:u0|Add0~138COUT1 fenpin:u0|Add0~140COUT1 fenpin:u0|Add0~144COUT1 fenpin:u0|Add0~146 fenpin:u0|Add0~149 fenpin:u0|cnt[7] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "4.075 ns" { saomiao:u2|cnt[0] fenpin:u0|Add0~136COUT1 fenpin:u0|Add0~138COUT1 fenpin:u0|Add0~140COUT1 fenpin:u0|Add0~144COUT1 fenpin:u0|Add0~146 fenpin:u0|Add0~149 fenpin:u0|cnt[7] } { 0.000ns 2.030ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.528ns } { 0.000ns 0.451ns 0.060ns 0.060ns 0.060ns 0.118ns 0.449ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.149 ns - Smallest " "Info: - Smallest clock skew is 0.149 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.052 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.052 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 10 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.682 ns) + CELL(0.542 ns) 3.052 ns fenpin:u0\|cnt\[7\] 2 REG LC_X1_Y15_N5 4 " "Info: 2: + IC(1.682 ns) + CELL(0.542 ns) = 3.052 ns; Loc. = LC_X1_Y15_N5; Fanout = 4; REG Node = 'fenpin:u0\|cnt\[7\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.224 ns" { clk fenpin:u0|cnt[7] } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.89 % ) " "Info: Total cell delay = 1.370 ns ( 44.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.682 ns ( 55.11 % ) " "Info: Total interconnect delay = 1.682 ns ( 55.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.052 ns" { clk fenpin:u0|cnt[7] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "3.052 ns" { clk clk~out0 fenpin:u0|cnt[7] } { 0.000ns 0.000ns 1.682ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.903 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 10 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.533 ns) + CELL(0.542 ns) 2.903 ns saomiao:u2\|cnt\[0\] 2 REG LC_X30_Y23_N5 11 " "Info: 2: + IC(1.533 ns) + CELL(0.542 ns) = 2.903 ns; Loc. = LC_X30_Y23_N5; Fanout = 11; REG Node = 'saomiao:u2\|cnt\[0\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.075 ns" { clk saomiao:u2|cnt[0] } "NODE_NAME" } } { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.19 % ) " "Info: Total cell delay = 1.370 ns ( 47.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.533 ns ( 52.81 % ) " "Info: Total interconnect delay = 1.533 ns ( 52.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.903 ns" { clk saomiao:u2|cnt[0] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 saomiao:u2|cnt[0] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.052 ns" { clk fenpin:u0|cnt[7] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "3.052 ns" { clk clk~out0 fenpin:u0|cnt[7] } { 0.000ns 0.000ns 1.682ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.903 ns" { clk saomiao:u2|cnt[0] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 saomiao:u2|cnt[0] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.075 ns" { saomiao:u2|cnt[0] fenpin:u0|Add0~136COUT1 fenpin:u0|Add0~138COUT1 fenpin:u0|Add0~140COUT1 fenpin:u0|Add0~144COUT1 fenpin:u0|Add0~146 fenpin:u0|Add0~149 fenpin:u0|cnt[7] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "4.075 ns" { saomiao:u2|cnt[0] fenpin:u0|Add0~136COUT1 fenpin:u0|Add0~138COUT1 fenpin:u0|Add0~140COUT1 fenpin:u0|Add0~144COUT1 fenpin:u0|Add0~146 fenpin:u0|Add0~149 fenpin:u0|cnt[7] } { 0.000ns 2.030ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.528ns } { 0.000ns 0.451ns 0.060ns 0.060ns 0.060ns 0.118ns 0.449ns 0.319ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.052 ns" { clk fenpin:u0|cnt[7] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "3.052 ns" { clk clk~out0 fenpin:u0|cnt[7] } { 0.000ns 0.000ns 1.682ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.903 ns" { clk saomiao:u2|cnt[0] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 saomiao:u2|cnt[0] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ctr:u1\|ch\[2\] stop clk 0.186 ns register " "Info: tsu for register \"ctr:u1\|ch\[2\]\" (data pin = \"stop\", clock pin = \"clk\") is 0.186 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.059 ns + Longest pin register " "Info: + Longest pin to register delay is 7.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns stop 1 PIN PIN_J8 21 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J8; Fanout = 21; PIN Node = 'stop'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { stop } "NODE_NAME" } } { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.906 ns) + CELL(0.366 ns) 5.359 ns ctr:u1\|ch\[1\]~735 2 COMB LC_X32_Y25_N5 1 " "Info: 2: + IC(3.906 ns) + CELL(0.366 ns) = 5.359 ns; Loc. = LC_X32_Y25_N5; Fanout = 1; COMB Node = 'ctr:u1\|ch\[1\]~735'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.272 ns" { stop ctr:u1|ch[1]~735 } "NODE_NAME" } } { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.341 ns) + CELL(0.183 ns) 5.883 ns ctr:u1\|ch\[1\]~737 3 COMB LC_X32_Y25_N4 4 " "Info: 3: + IC(0.341 ns) + CELL(0.183 ns) = 5.883 ns; Loc. = LC_X32_Y25_N4; Fanout = 4; COMB Node = 'ctr:u1\|ch\[1\]~737'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.524 ns" { ctr:u1|ch[1]~735 ctr:u1|ch[1]~737 } "NODE_NAME" } } { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.471 ns) + CELL(0.705 ns) 7.059 ns ctr:u1\|ch\[2\] 4 REG LC_X33_Y25_N8 4 " "Info: 4: + IC(0.471 ns) + CELL(0.705 ns) = 7.059 ns; Loc. = LC_X33_Y25_N8; Fanout = 4; REG Node = 'ctr:u1\|ch\[2\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.176 ns" { ctr:u1|ch[1]~737 ctr:u1|ch[2] } "NODE_NAME" } } { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.341 ns ( 33.16 % ) " "Info: Total cell delay = 2.341 ns ( 33.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.718 ns ( 66.84 % ) " "Info: Total interconnect delay = 4.718 ns ( 66.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "7.059 ns" { stop ctr:u1|ch[1]~735 ctr:u1|ch[1]~737 ctr:u1|ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "7.059 ns" { stop stop~out0 ctr:u1|ch[1]~735 ctr:u1|ch[1]~737 ctr:u1|ch[2] } { 0.000ns 0.000ns 3.906ns 0.341ns 0.471ns } { 0.000ns 1.087ns 0.366ns 0.183ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.883 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.883 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 10 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.682 ns) + CELL(0.698 ns) 3.208 ns fenpin:u0\|q 2 REG LC_X1_Y15_N7 26 " "Info: 2: + IC(1.682 ns) + CELL(0.698 ns) = 3.208 ns; Loc. = LC_X1_Y15_N7; Fanout = 26; REG Node = 'fenpin:u0\|q'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.380 ns" { clk fenpin:u0|q } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.133 ns) + CELL(0.542 ns) 6.883 ns ctr:u1\|ch\[2\] 3 REG LC_X33_Y25_N8 4 " "Info: 3: + IC(3.133 ns) + CELL(0.542 ns) = 6.883 ns; Loc. = LC_X33_Y25_N8; Fanout = 4; REG Node = 'ctr:u1\|ch\[2\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.675 ns" { fenpin:u0|q ctr:u1|ch[2] } "NODE_NAME" } } { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns ( 30.05 % ) " "Info: Total cell delay = 2.068 ns ( 30.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.815 ns ( 69.95 % ) " "Info: Total interconnect delay = 4.815 ns ( 69.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "6.883 ns" { clk fenpin:u0|q ctr:u1|ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "6.883 ns" { clk clk~out0 fenpin:u0|q ctr:u1|ch[2] } { 0.000ns 0.000ns 1.682ns 3.133ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "7.059 ns" { stop ctr:u1|ch[1]~735 ctr:u1|ch[1]~737 ctr:u1|ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "7.059 ns" { stop stop~out0 ctr:u1|ch[1]~735 ctr:u1|ch[1]~737 ctr:u1|ch[2] } { 0.000ns 0.000ns 3.906ns 0.341ns 0.471ns } { 0.000ns 1.087ns 0.366ns 0.183ns 0.705ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "6.883 ns" { clk fenpin:u0|q ctr:u1|ch[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "6.883 ns" { clk clk~out0 fenpin:u0|q ctr:u1|ch[2] } { 0.000ns 0.000ns 1.682ns 3.133ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg\[2\] ctr:u1\|cl\[0\] 15.086 ns register " "Info: tco from clock \"clk\" to destination pin \"seg\[2\]\" through register \"ctr:u1\|cl\[0\]\" is 15.086 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.883 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.883 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 10 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.682 ns) + CELL(0.698 ns) 3.208 ns fenpin:u0\|q 2 REG LC_X1_Y15_N7 26 " "Info: 2: + IC(1.682 ns) + CELL(0.698 ns) = 3.208 ns; Loc. = LC_X1_Y15_N7; Fanout = 26; REG Node = 'fenpin:u0\|q'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.380 ns" { clk fenpin:u0|q } "NODE_NAME" } } { "../fenpin/fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.133 ns) + CELL(0.542 ns) 6.883 ns ctr:u1\|cl\[0\] 3 REG LC_X31_Y25_N5 9 " "Info: 3: + IC(3.133 ns) + CELL(0.542 ns) = 6.883 ns; Loc. = LC_X31_Y25_N5; Fanout = 9; REG Node = 'ctr:u1\|cl\[0\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.675 ns" { fenpin:u0|q ctr:u1|cl[0] } "NODE_NAME" } } { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns ( 30.05 % ) " "Info: Total cell delay = 2.068 ns ( 30.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.815 ns ( 69.95 % ) " "Info: Total interconnect delay = 4.815 ns ( 69.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "6.883 ns" { clk fenpin:u0|q ctr:u1|cl[0] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "6.883 ns" { clk clk~out0 fenpin:u0|q ctr:u1|cl[0] } { 0.000ns 0.000ns 1.682ns 3.133ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.047 ns + Longest register pin " "Info: + Longest register to pin delay is 8.047 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ctr:u1\|cl\[0\] 1 REG LC_X31_Y25_N5 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y25_N5; Fanout = 9; REG Node = 'ctr:u1\|cl\[0\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctr:u1|cl[0] } "NODE_NAME" } } { "../state/Vhdl1.vhd" "" { Text "E:/vhd/jiaotongdeng/state/Vhdl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.183 ns) 1.044 ns saomiao:u2\|Mux3~14 2 COMB LC_X33_Y25_N0 7 " "Info: 2: + IC(0.861 ns) + CELL(0.183 ns) = 1.044 ns; Loc. = LC_X33_Y25_N0; Fanout = 7; COMB Node = 'saomiao:u2\|Mux3~14'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.044 ns" { ctr:u1|cl[0] saomiao:u2|Mux3~14 } "NODE_NAME" } } { "../scan/saomiao.vhd" "" { Text "E:/vhd/jiaotongdeng/scan/saomiao.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.251 ns) + CELL(0.366 ns) 2.661 ns display:u3\|Mux4~25 3 COMB LC_X30_Y23_N4 1 " "Info: 3: + IC(1.251 ns) + CELL(0.366 ns) = 2.661 ns; Loc. = LC_X30_Y23_N4; Fanout = 1; COMB Node = 'display:u3\|Mux4~25'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.617 ns" { saomiao:u2|Mux3~14 display:u3|Mux4~25 } "NODE_NAME" } } { "../display/display.vhd" "" { Text "E:/vhd/jiaotongdeng/display/display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.323 ns) + CELL(0.366 ns) 3.350 ns dplay:u4\|seg\[2\]~247 4 COMB LC_X30_Y23_N0 1 " "Info: 4: + IC(0.323 ns) + CELL(0.366 ns) = 3.350 ns; Loc. = LC_X30_Y23_N0; Fanout = 1; COMB Node = 'dplay:u4\|seg\[2\]~247'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.689 ns" { display:u3|Mux4~25 dplay:u4|seg[2]~247 } "NODE_NAME" } } { "../xianshi/dplay.vhd" "" { Text "E:/vhd/jiaotongdeng/xianshi/dplay.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.293 ns) + CELL(2.404 ns) 8.047 ns seg\[2\] 5 PIN PIN_N10 0 " "Info: 5: + IC(2.293 ns) + CELL(2.404 ns) = 8.047 ns; Loc. = PIN_N10; Fanout = 0; PIN Node = 'seg\[2\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.697 ns" { dplay:u4|seg[2]~247 seg[2] } "NODE_NAME" } } { "traffic_lights.vhd" "" { Text "E:/vhd/jiaotongdeng/traffic_lights/traffic_lights.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.319 ns ( 41.25 % ) " "Info: Total cell delay = 3.319 ns ( 41.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.728 ns ( 58.75 % ) " "Info: Total interconnect delay = 4.728 ns ( 58.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "8.047 ns" { ctr:u1|cl[0] saomiao:u2|Mux3~14 display:u3|Mux4~25 dplay:u4|seg[2]~247 seg[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "8.047 ns" { ctr:u1|cl[0] saomiao:u2|Mux3~14 display:u3|Mux4~25 dplay:u4|seg[2]~247 seg[2] } { 0.000ns 0.861ns 1.251ns 0.323ns 2.293ns } { 0.000ns 0.183ns 0.366ns 0.366ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "6.883 ns" { clk fenpin:u0|q ctr:u1|cl[0] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "6.883 ns" { clk clk~out0 fenpin:u0|q ctr:u1|cl[0] } { 0.000ns 0.000ns 1.682ns 3.133ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "8.047 ns" { ctr:u1|cl[0] saomiao:u2|Mux3~14 display:u3|Mux4~25 dplay:u4|seg[2]~247 seg[2] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "8.047 ns" { ctr:u1|cl[0] saomiao:u2|Mux3~14 display:u3|Mux4~25 dplay:u4|seg[2]~247 seg[2] } { 0.000ns 0.861ns 1.251ns 0.323ns 2.293ns } { 0.000ns 0.183ns 0.366ns 0.366ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}