📄 traffic_lights.map.rpt
字号:
; ; ;
; Total registers ; 28 ;
; Total logic cells in carry chains ; 8 ;
; I/O pins ; 0 ;
; Maximum fan-out node ; fenpin:u0|q ;
; Maximum fan-out ; 26 ;
; Total fan-out ; 316 ;
; Average fan-out ; 3.01 ;
+---------------------------------------------+-------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
; |traffic_lights ; 88 (0) ; 28 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 60 (0) ; 6 (0) ; 22 (0) ; 8 (0) ; 0 (0) ; |traffic_lights ;
; |ctr:u1| ; 43 (43) ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 25 (25) ; 4 (4) ; 14 (14) ; 0 (0) ; 0 (0) ; |traffic_lights|ctr:u1 ;
; |display:u3| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |traffic_lights|display:u3 ;
; |dplay:u4| ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |traffic_lights|dplay:u4 ;
; |fenpin:u0| ; 19 (19) ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 2 (2) ; 7 (7) ; 8 (8) ; 0 (0) ; |traffic_lights|fenpin:u0 ;
; |saomiao:u2| ; 6 (6) ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |traffic_lights|saomiao:u2 ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+-----------------------------------------------------------+
; State Machine - |traffic_lights|ctr:u1|stax ;
+-----------+-----------+-----------+-----------+-----------+
; Name ; stax.sta4 ; stax.sta3 ; stax.sta2 ; stax.sta1 ;
+-----------+-----------+-----------+-----------+-----------+
; stax.sta1 ; 0 ; 0 ; 0 ; 0 ;
; stax.sta2 ; 0 ; 0 ; 1 ; 1 ;
; stax.sta3 ; 0 ; 1 ; 0 ; 1 ;
; stax.sta4 ; 1 ; 0 ; 0 ; 1 ;
+-----------+-----------+-----------+-----------+-----------+
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; u1/r2 ; Merged with u1/r1 ;
; u0/cnt[0] ; Merged with u2/cnt[0] ;
; u2/cnt[1] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 3 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 28 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 1 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 16 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 6:1 ; 2 bits ; 8 LEs ; 2 LEs ; 6 LEs ; Yes ; |traffic_lights|ctr:u1|r2 ;
; 13:1 ; 4 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |traffic_lights|ctr:u1|ch[1] ;
; 13:1 ; 4 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |traffic_lights|ctr:u1|cl[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Sat Nov 15 22:03:08 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic_lights -c traffic_lights
Info: Found 2 design units, including 1 entities, in source file ../xianshi/dplay.vhd
Info: Found design unit 1: dplay-one
Info: Found entity 1: dplay
Info: Found 2 design units, including 1 entities, in source file ../state/Vhdl1.vhd
Info: Found design unit 1: ctr-one
Info: Found entity 1: ctr
Info: Found 2 design units, including 1 entities, in source file ../scan/saomiao.vhd
Info: Found design unit 1: saomiao-one
Info: Found entity 1: saomiao
Info: Found 2 design units, including 1 entities, in source file ../fenpin/fenpin.vhd
Info: Found design unit 1: fenpin-one
Info: Found entity 1: fenpin
Info: Found 2 design units, including 1 entities, in source file ../display/display.vhd
Info: Found design unit 1: display-one
Info: Found entity 1: display
Info: Found 2 design units, including 1 entities, in source file traffic_lights.vhd
Info: Found design unit 1: traffic_lights-rtl
Info: Found entity 1: traffic_lights
Info: Elaborating entity "traffic_lights" for the top level hierarchy
Info: Elaborating entity "fenpin" for hierarchy "fenpin:u0"
Info: Elaborating entity "ctr" for hierarchy "ctr:u1"
Info: Elaborating entity "saomiao" for hierarchy "saomiao:u2"
Warning (10492): VHDL Process Statement warning at saomiao.vhd(31): signal "d" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at saomiao.vhd(24): inferring latch(es) for signal or variable "d", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at saomiao.vhd(24): inferring latch(es) for signal or variable "adr", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "adr[0]"
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "adr[1]"
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "d[0]"
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "d[1]"
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "d[2]"
Info (10041): Verilog HDL or VHDL info at saomiao.vhd(24): inferred latch for "d[3]"
Info: Elaborating entity "display" for hierarchy "display:u3"
Info: Elaborating entity "dplay" for hierarchy "dplay:u4"
Warning (10492): VHDL Process Statement warning at dplay.vhd(25): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at dplay.vhd(26): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at dplay.vhd(27): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at dplay.vhd(28): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at dplay.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at dplay.vhd(30): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at dplay.vhd(31): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Duplicate registers merged to single register
Info: Duplicate register "ctr:u1|r2" merged to single register "ctr:u1|r1", power-up level changed
Info: State machine "|traffic_lights|ctr:u1|stax" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|traffic_lights|ctr:u1|stax"
Info: Encoding result for state machine "|traffic_lights|ctr:u1|stax"
Info: Completed encoding using 4 state bits
Info: Encoded state bit "ctr:u1|stax.sta4"
Info: Encoded state bit "ctr:u1|stax.sta3"
Info: Encoded state bit "ctr:u1|stax.sta2"
Info: Encoded state bit "ctr:u1|stax.sta1"
Info: State "|traffic_lights|ctr:u1|stax.sta1" uses code string "0000"
Info: State "|traffic_lights|ctr:u1|stax.sta2" uses code string "0011"
Info: State "|traffic_lights|ctr:u1|stax.sta3" uses code string "0101"
Info: State "|traffic_lights|ctr:u1|stax.sta4" uses code string "1001"
Info: Duplicate registers merged to single register
Info: Duplicate register "fenpin:u0|cnt[0]" merged to single register "saomiao:u2|cnt[0]"
Warning: Reduced register "saomiao:u2|cnt[1]" with stuck data_in port to stuck value GND
Warning: LATCH primitive "saomiao:u2|adr[0]" is permanently enabled
Warning: LATCH primitive "saomiao:u2|adr[1]" is permanently enabled
Warning: LATCH primitive "saomiao:u2|d[0]" is permanently enabled
Warning: LATCH primitive "saomiao:u2|d[1]" is permanently enabled
Warning: LATCH primitive "saomiao:u2|d[2]" is permanently enabled
Warning: LATCH primitive "saomiao:u2|d[3]" is permanently enabled
Info: Implemented 105 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 15 output pins
Info: Implemented 88 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings
Info: Allocated 140 megabytes of memory during processing
Info: Processing ended: Sat Nov 15 22:03:11 2008
Info: Elapsed time: 00:00:03
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