📄 dplay.tan.rpt
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Classic Timing Analyzer report for dplay
Sat Nov 15 21:32:58 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 10.120 ns ; stop ; sny ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+----------+--------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+----------+--------+
; N/A ; None ; 10.120 ns ; stop ; sny ;
; N/A ; None ; 10.117 ns ; stop ; seg[0] ;
; N/A ; None ; 10.111 ns ; stop ; ewg ;
; N/A ; None ; 10.095 ns ; stop ; sng ;
; N/A ; None ; 10.093 ns ; stop ; snr ;
; N/A ; None ; 10.092 ns ; stop ; seg[2] ;
; N/A ; None ; 9.897 ns ; stop ; seg[1] ;
; N/A ; None ; 9.896 ns ; stop ; ewr ;
; N/A ; None ; 9.886 ns ; stop ; ewy ;
; N/A ; None ; 9.883 ns ; stop ; seg[3] ;
; N/A ; None ; 9.622 ns ; clk ; seg[5] ;
; N/A ; None ; 9.622 ns ; clk ; seg[4] ;
; N/A ; None ; 9.618 ns ; clk ; seg[6] ;
; N/A ; None ; 9.581 ns ; stop ; seg[5] ;
; N/A ; None ; 9.580 ns ; stop ; seg[4] ;
; N/A ; None ; 9.576 ns ; stop ; seg[6] ;
; N/A ; None ; 8.976 ns ; clk ; seg[0] ;
; N/A ; None ; 8.961 ns ; clk ; seg[2] ;
; N/A ; None ; 8.911 ns ; segin[2] ; seg[2] ;
; N/A ; None ; 8.890 ns ; r2_t ; sny ;
; N/A ; None ; 8.853 ns ; r1_t ; snr ;
; N/A ; None ; 8.751 ns ; clk ; seg[3] ;
; N/A ; None ; 8.751 ns ; clk ; seg[1] ;
; N/A ; None ; 8.714 ns ; g2_t ; ewg ;
; N/A ; None ; 8.674 ns ; y1_t ; sng ;
; N/A ; None ; 8.668 ns ; segin[0] ; seg[0] ;
; N/A ; None ; 8.601 ns ; y2_t ; ewy ;
; N/A ; None ; 8.580 ns ; segin[3] ; seg[3] ;
; N/A ; None ; 8.484 ns ; segin[1] ; seg[1] ;
; N/A ; None ; 8.383 ns ; segin[6] ; seg[6] ;
; N/A ; None ; 8.381 ns ; segin[4] ; seg[4] ;
; N/A ; None ; 8.372 ns ; segin[5] ; seg[5] ;
; N/A ; None ; 8.324 ns ; g1_t ; ewr ;
+-------+-------------------+-----------------+----------+--------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Sat Nov 15 21:32:57 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dplay -c dplay --timing_analysis_only
Info: Longest tpd from source pin "stop" to destination pin "sny" is 10.120 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_E17; Fanout = 13; PIN Node = 'stop'
Info: 2: + IC(4.916 ns) + CELL(0.366 ns) = 6.369 ns; Loc. = LC_X5_Y1_N2; Fanout = 1; COMB Node = 'sny~11'
Info: 3: + IC(1.347 ns) + CELL(2.404 ns) = 10.120 ns; Loc. = PIN_W18; Fanout = 0; PIN Node = 'sny'
Info: Total cell delay = 3.857 ns ( 38.11 % )
Info: Total interconnect delay = 6.263 ns ( 61.89 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 100 megabytes of memory during processing
Info: Processing ended: Sat Nov 15 21:32:58 2008
Info: Elapsed time: 00:00:01
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