fenpin.tan.qmsg

vhdl的铜须等

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[0\] register cnt\[5\] 396.83 MHz 2.52 ns Internal " "Info: Clock \"clk\" has Internal fmax of 396.83 MHz between source register \"cnt\[0\]\" and destination register \"cnt\[5\]\" (period= 2.52 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.354 ns + Longest register register " "Info: + Longest register to register delay is 2.354 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LC_X31_Y22_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y22_N8; Fanout = 4; REG Node = 'cnt\[0\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.526 ns) + CELL(0.344 ns) 0.870 ns Add0~133 2 COMB LC_X30_Y22_N0 2 " "Info: 2: + IC(0.526 ns) + CELL(0.344 ns) = 0.870 ns; Loc. = LC_X30_Y22_N0; Fanout = 2; COMB Node = 'Add0~133'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.870 ns" { cnt[0] Add0~133 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 0.928 ns Add0~135 3 COMB LC_X30_Y22_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 0.928 ns; Loc. = LC_X30_Y22_N1; Fanout = 2; COMB Node = 'Add0~135'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { Add0~133 Add0~135 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 0.986 ns Add0~137 4 COMB LC_X30_Y22_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 0.986 ns; Loc. = LC_X30_Y22_N2; Fanout = 2; COMB Node = 'Add0~137'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { Add0~135 Add0~137 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 1.044 ns Add0~139 5 COMB LC_X30_Y22_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 1.044 ns; Loc. = LC_X30_Y22_N3; Fanout = 2; COMB Node = 'Add0~139'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { Add0~137 Add0~139 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.130 ns) 1.174 ns Add0~143 6 COMB LC_X30_Y22_N4 4 " "Info: 6: + IC(0.000 ns) + CELL(0.130 ns) = 1.174 ns; Loc. = LC_X30_Y22_N4; Fanout = 4; COMB Node = 'Add0~143'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.130 ns" { Add0~139 Add0~143 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 1.623 ns Add0~144 7 COMB LC_X30_Y22_N5 1 " "Info: 7: + IC(0.000 ns) + CELL(0.449 ns) = 1.623 ns; Loc. = LC_X30_Y22_N5; Fanout = 1; COMB Node = 'Add0~144'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.449 ns" { Add0~143 Add0~144 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.508 ns) + CELL(0.223 ns) 2.354 ns cnt\[5\] 8 REG LC_X31_Y22_N7 4 " "Info: 8: + IC(0.508 ns) + CELL(0.223 ns) = 2.354 ns; Loc. = LC_X31_Y22_N7; Fanout = 4; REG Node = 'cnt\[5\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.731 ns" { Add0~144 cnt[5] } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 56.07 % ) " "Info: Total cell delay = 1.320 ns ( 56.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.034 ns ( 43.93 % ) " "Info: Total interconnect delay = 1.034 ns ( 43.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.354 ns" { cnt[0] Add0~133 Add0~135 Add0~137 Add0~139 Add0~143 Add0~144 cnt[5] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.354 ns" { cnt[0] Add0~133 Add0~135 Add0~137 Add0~139 Add0~143 Add0~144 cnt[5] } { 0.000ns 0.526ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.508ns } { 0.000ns 0.344ns 0.058ns 0.058ns 0.058ns 0.130ns 0.449ns 0.223ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.909 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 10 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.539 ns) + CELL(0.542 ns) 2.909 ns cnt\[5\] 2 REG LC_X31_Y22_N7 4 " "Info: 2: + IC(1.539 ns) + CELL(0.542 ns) = 2.909 ns; Loc. = LC_X31_Y22_N7; Fanout = 4; REG Node = 'cnt\[5\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.081 ns" { clk cnt[5] } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.10 % ) " "Info: Total cell delay = 1.370 ns ( 47.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.539 ns ( 52.90 % ) " "Info: Total interconnect delay = 1.539 ns ( 52.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk cnt[5] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 cnt[5] } { 0.000ns 0.000ns 1.539ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.909 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 10 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.539 ns) + CELL(0.542 ns) 2.909 ns cnt\[0\] 2 REG LC_X31_Y22_N8 4 " "Info: 2: + IC(1.539 ns) + CELL(0.542 ns) = 2.909 ns; Loc. = LC_X31_Y22_N8; Fanout = 4; REG Node = 'cnt\[0\]'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.081 ns" { clk cnt[0] } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.10 % ) " "Info: Total cell delay = 1.370 ns ( 47.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.539 ns ( 52.90 % ) " "Info: Total interconnect delay = 1.539 ns ( 52.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk cnt[0] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 cnt[0] } { 0.000ns 0.000ns 1.539ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk cnt[5] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 cnt[5] } { 0.000ns 0.000ns 1.539ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk cnt[0] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 cnt[0] } { 0.000ns 0.000ns 1.539ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.354 ns" { cnt[0] Add0~133 Add0~135 Add0~137 Add0~139 Add0~143 Add0~144 cnt[5] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.354 ns" { cnt[0] Add0~133 Add0~135 Add0~137 Add0~139 Add0~143 Add0~144 cnt[5] } { 0.000ns 0.526ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.508ns } { 0.000ns 0.344ns 0.058ns 0.058ns 0.058ns 0.130ns 0.449ns 0.223ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk cnt[5] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 cnt[5] } { 0.000ns 0.000ns 1.539ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk cnt[0] } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 cnt[0] } { 0.000ns 0.000ns 1.539ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk1hz q 7.033 ns register " "Info: tco from clock \"clk\" to destination pin \"clk1hz\" through register \"q\" is 7.033 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.909 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 10 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.539 ns) + CELL(0.542 ns) 2.909 ns q 2 REG LC_X31_Y22_N4 2 " "Info: 2: + IC(1.539 ns) + CELL(0.542 ns) = 2.909 ns; Loc. = LC_X31_Y22_N4; Fanout = 2; REG Node = 'q'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.081 ns" { clk q } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.10 % ) " "Info: Total cell delay = 1.370 ns ( 47.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.539 ns ( 52.90 % ) " "Info: Total interconnect delay = 1.539 ns ( 52.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk q } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 q } { 0.000ns 0.000ns 1.539ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.968 ns + Longest register pin " "Info: + Longest register to pin delay is 3.968 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q 1 REG LC_X31_Y22_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y22_N4; Fanout = 2; REG Node = 'q'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { q } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(2.404 ns) 3.968 ns clk1hz 2 PIN PIN_K10 0 " "Info: 2: + IC(1.564 ns) + CELL(2.404 ns) = 3.968 ns; Loc. = PIN_K10; Fanout = 0; PIN Node = 'clk1hz'" {  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.968 ns" { q clk1hz } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/vhd/jiaotongdeng/fenpin/fenpin.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 60.58 % ) " "Info: Total cell delay = 2.404 ns ( 60.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.564 ns ( 39.42 % ) " "Info: Total interconnect delay = 1.564 ns ( 39.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.968 ns" { q clk1hz } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "3.968 ns" { q clk1hz } { 0.000ns 1.564ns } { 0.000ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk q } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 q } { 0.000ns 0.000ns 1.539ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/peogram files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.968 ns" { q clk1hz } "NODE_NAME" } } { "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/peogram files/alter/quartus/bin/Technology_Viewer.qrui" "3.968 ns" { q clk1hz } { 0.000ns 1.564ns } { 0.000ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "99 " "Info: Allocated 99 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 14 21:22:33 2008 " "Info: Processing ended: Fri Nov 14 21:22:33 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}