📄 fenpin.tan.rpt
字号:
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[7] ; cnt[8] ; clk ; clk ; None ; None ; 1.956 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; cnt[1] ; clk ; clk ; None ; None ; 1.942 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[1] ; cnt[2] ; clk ; clk ; None ; None ; 1.942 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; cnt[3] ; clk ; clk ; None ; None ; 1.932 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[3] ; cnt[4] ; clk ; clk ; None ; None ; 1.925 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[5] ; cnt[5] ; clk ; clk ; None ; None ; 1.893 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[5] ; q ; clk ; clk ; None ; None ; 1.890 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[5] ; cnt[4] ; clk ; clk ; None ; None ; 1.886 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[1] ; cnt[3] ; clk ; clk ; None ; None ; 1.871 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[2] ; cnt[8] ; clk ; clk ; None ; None ; 1.845 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[1] ; q ; clk ; clk ; None ; None ; 1.823 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[2] ; cnt[3] ; clk ; clk ; None ; None ; 1.793 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[3] ; cnt[8] ; clk ; clk ; None ; None ; 1.790 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[6] ; cnt[8] ; clk ; clk ; None ; None ; 1.786 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[5] ; cnt[2] ; clk ; clk ; None ; None ; 1.772 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[4] ; cnt[8] ; clk ; clk ; None ; None ; 1.763 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[7] ; cnt[7] ; clk ; clk ; None ; None ; 1.740 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[7] ; cnt[5] ; clk ; clk ; None ; None ; 1.739 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[7] ; q ; clk ; clk ; None ; None ; 1.736 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[7] ; cnt[6] ; clk ; clk ; None ; None ; 1.734 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[7] ; cnt[4] ; clk ; clk ; None ; None ; 1.732 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; cnt[0] ; clk ; clk ; None ; None ; 1.635 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[6] ; cnt[6] ; clk ; clk ; None ; None ; 1.631 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[7] ; cnt[2] ; clk ; clk ; None ; None ; 1.618 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[2] ; cnt[2] ; clk ; clk ; None ; None ; 1.590 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[2] ; q ; clk ; clk ; None ; None ; 1.587 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[1] ; cnt[1] ; clk ; clk ; None ; None ; 1.515 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[4] ; cnt[4] ; clk ; clk ; None ; None ; 1.503 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[6] ; cnt[5] ; clk ; clk ; None ; None ; 1.400 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[6] ; q ; clk ; clk ; None ; None ; 1.397 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[6] ; cnt[4] ; clk ; clk ; None ; None ; 1.393 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[3] ; cnt[2] ; clk ; clk ; None ; None ; 1.392 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[3] ; q ; clk ; clk ; None ; None ; 1.389 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[3] ; cnt[3] ; clk ; clk ; None ; None ; 1.370 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[4] ; q ; clk ; clk ; None ; None ; 1.310 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[6] ; cnt[2] ; clk ; clk ; None ; None ; 1.279 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[4] ; cnt[2] ; clk ; clk ; None ; None ; 1.192 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; q ; clk ; clk ; None ; None ; 1.157 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[8] ; cnt[2] ; clk ; clk ; None ; None ; 1.051 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[8] ; cnt[4] ; clk ; clk ; None ; None ; 0.929 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[8] ; cnt[6] ; clk ; clk ; None ; None ; 0.928 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[8] ; q ; clk ; clk ; None ; None ; 0.927 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[8] ; cnt[5] ; clk ; clk ; None ; None ; 0.922 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[8] ; cnt[7] ; clk ; clk ; None ; None ; 0.920 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[8] ; cnt[8] ; clk ; clk ; None ; None ; 0.841 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; q ; q ; clk ; clk ; None ; None ; 0.642 ns ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
+----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+--------+------------+
; N/A ; None ; 7.033 ns ; q ; clk1hz ; clk ;
+-------+--------------+------------+------+--------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Fri Nov 14 21:22:33 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fenpin -c fenpin --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 396.83 MHz between source register "cnt[0]" and destination register "cnt[5]" (period= 2.52 ns)
Info: + Longest register to register delay is 2.354 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y22_N8; Fanout = 4; REG Node = 'cnt[0]'
Info: 2: + IC(0.526 ns) + CELL(0.344 ns) = 0.870 ns; Loc. = LC_X30_Y22_N0; Fanout = 2; COMB Node = 'Add0~133'
Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 0.928 ns; Loc. = LC_X30_Y22_N1; Fanout = 2; COMB Node = 'Add0~135'
Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 0.986 ns; Loc. = LC_X30_Y22_N2; Fanout = 2; COMB Node = 'Add0~137'
Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 1.044 ns; Loc. = LC_X30_Y22_N3; Fanout = 2; COMB Node = 'Add0~139'
Info: 6: + IC(0.000 ns) + CELL(0.130 ns) = 1.174 ns; Loc. = LC_X30_Y22_N4; Fanout = 4; COMB Node = 'Add0~143'
Info: 7: + IC(0.000 ns) + CELL(0.449 ns) = 1.623 ns; Loc. = LC_X30_Y22_N5; Fanout = 1; COMB Node = 'Add0~144'
Info: 8: + IC(0.508 ns) + CELL(0.223 ns) = 2.354 ns; Loc. = LC_X31_Y22_N7; Fanout = 4; REG Node = 'cnt[5]'
Info: Total cell delay = 1.320 ns ( 56.07 % )
Info: Total interconnect delay = 1.034 ns ( 43.93 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.909 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 10; CLK Node = 'clk'
Info: 2: + IC(1.539 ns) + CELL(0.542 ns) = 2.909 ns; Loc. = LC_X31_Y22_N7; Fanout = 4; REG Node = 'cnt[5]'
Info: Total cell delay = 1.370 ns ( 47.10 % )
Info: Total interconnect delay = 1.539 ns ( 52.90 % )
Info: - Longest clock path from clock "clk" to source register is 2.909 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 10; CLK Node = 'clk'
Info: 2: + IC(1.539 ns) + CELL(0.542 ns) = 2.909 ns; Loc. = LC_X31_Y22_N8; Fanout = 4; REG Node = 'cnt[0]'
Info: Total cell delay = 1.370 ns ( 47.10 % )
Info: Total interconnect delay = 1.539 ns ( 52.90 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock "clk" to destination pin "clk1hz" through register "q" is 7.033 ns
Info: + Longest clock path from clock "clk" to source register is 2.909 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 10; CLK Node = 'clk'
Info: 2: + IC(1.539 ns) + CELL(0.542 ns) = 2.909 ns; Loc. = LC_X31_Y22_N4; Fanout = 2; REG Node = 'q'
Info: Total cell delay = 1.370 ns ( 47.10 % )
Info: Total interconnect delay = 1.539 ns ( 52.90 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Longest register to pin delay is 3.968 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y22_N4; Fanout = 2; REG Node = 'q'
Info: 2: + IC(1.564 ns) + CELL(2.404 ns) = 3.968 ns; Loc. = PIN_K10; Fanout = 0; PIN Node = 'clk1hz'
Info: Total cell delay = 2.404 ns ( 60.58 % )
Info: Total interconnect delay = 1.564 ns ( 39.42 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 99 megabytes of memory during processing
Info: Processing ended: Fri Nov 14 21:22:33 2008
Info: Elapsed time: 00:00:00
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