fenpin.tan.rpt

vhdl的铜须等

Classic Timing Analyzer report for fenpin
Fri Nov 14 21:22:33 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                          ;
+------------------------------+-------+---------------+----------------------------------+--------+--------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From   ; To     ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------+--------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 7.033 ns                         ; q      ; clk1hz ; clk        ; --       ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 396.83 MHz ( period = 2.520 ns ) ; cnt[0] ; cnt[5] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;        ;        ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------+--------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                   ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From   ; To     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 396.83 MHz ( period = 2.520 ns )               ; cnt[0] ; cnt[5] ; clk        ; clk      ; None                        ; None                      ; 2.354 ns                ;
; N/A   ; 398.25 MHz ( period = 2.511 ns )               ; cnt[0] ; cnt[7] ; clk        ; clk      ; None                        ; None                      ; 2.345 ns                ;
; N/A   ; 399.84 MHz ( period = 2.501 ns )               ; cnt[0] ; cnt[6] ; clk        ; clk      ; None                        ; None                      ; 2.335 ns                ;
; N/A   ; 406.34 MHz ( period = 2.461 ns )               ; cnt[1] ; cnt[5] ; clk        ; clk      ; None                        ; None                      ; 2.295 ns                ;
; N/A   ; 407.83 MHz ( period = 2.452 ns )               ; cnt[1] ; cnt[7] ; clk        ; clk      ; None                        ; None                      ; 2.286 ns                ;
; N/A   ; 408.33 MHz ( period = 2.449 ns )               ; cnt[5] ; cnt[7] ; clk        ; clk      ; None                        ; None                      ; 2.283 ns                ;
; N/A   ; 409.50 MHz ( period = 2.442 ns )               ; cnt[1] ; cnt[6] ; clk        ; clk      ; None                        ; None                      ; 2.276 ns                ;
; N/A   ; 419.29 MHz ( period = 2.385 ns )               ; cnt[2] ; cnt[5] ; clk        ; clk      ; None                        ; None                      ; 2.219 ns                ;
; N/A   ; 420.34 MHz ( period = 2.379 ns )               ; cnt[5] ; cnt[6] ; clk        ; clk      ; None                        ; None                      ; 2.213 ns                ;
; N/A   ; 420.88 MHz ( period = 2.376 ns )               ; cnt[2] ; cnt[7] ; clk        ; clk      ; None                        ; None                      ; 2.210 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[2] ; cnt[6] ; clk        ; clk      ; None                        ; None                      ; 2.200 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[3] ; cnt[5] ; clk        ; clk      ; None                        ; None                      ; 2.164 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[3] ; cnt[7] ; clk        ; clk      ; None                        ; None                      ; 2.155 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[3] ; cnt[6] ; clk        ; clk      ; None                        ; None                      ; 2.145 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[4] ; cnt[5] ; clk        ; clk      ; None                        ; None                      ; 2.137 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[4] ; cnt[7] ; clk        ; clk      ; None                        ; None                      ; 2.128 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; cnt[4] ; clk        ; clk      ; None                        ; None                      ; 2.121 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[4] ; cnt[6] ; clk        ; clk      ; None                        ; None                      ; 2.118 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[5] ; cnt[8] ; clk        ; clk      ; None                        ; None                      ; 2.110 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[6] ; cnt[7] ; clk        ; clk      ; None                        ; None                      ; 2.091 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[1] ; cnt[4] ; clk        ; clk      ; None                        ; None                      ; 2.060 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; cnt[2] ; clk        ; clk      ; None                        ; None                      ; 2.003 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[2] ; cnt[4] ; clk        ; clk      ; None                        ; None                      ; 1.982 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; cnt[8] ; clk        ; clk      ; None                        ; None                      ; 1.980 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[1] ; cnt[8] ; clk        ; clk      ; None                        ; None                      ; 1.962 ns                ;