vmeter.vhd

关于电压表的一个VHDL程序

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:18:08 12/13/2008 
-- Design Name: 
-- Module Name:    vmeter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vmeter is
port(	clk:in std_logic;
		scanclk:in std_logic;
		cmp: in std_logic;
		row:inout std_logic_vector(2 downto 0);
		led:out std_logic_vector(6 downto 0);
		led8:out std_logic;
		da:inout std_logic_vector(7 downto 0);
		da1:inout std_logic_vector(7 downto 0));
end vmeter;

architecture Behavioral of vmeter is

signal shift:std_logic_vector(8 downto 0);
signal bcd,bcd1,bcd2,bcd3:std_logic_vector(3 downto 0);
signal bcd11,bcd12,bcd13:std_logic_vector(3 downto 0);
signal tempdata:std_logic_vector(7 downto 0);
signal cclk,en,start,eoc,c1,c2:std_logic;

begin

	P1:process(clk, start)
	begin
		if rising_edge(clk) then
			if start = '1' or (shift /= "000000001" and shift /= "000000010"
					and shift /= "000000100" and shift /= "000001000"
					and shift /= "000010000" and shift /= "000100000"
					and shift /= "001000000" and shift /= "010000000"
					and shift /= "100000000") then 
				shift <= "100000000";
				eoc <= '0';
				elsif shift(0) = '1' then
					eoc <= '1';
					else
						shift <= '0'&shift(8 downto 1);
						eoc <= '0';
			end if;
		end if;
	end process;
	
	P2:process(clk, start, shift)
	begin
		if rising_edge(clk) then
			if start = '1' then
				da <= "00000000";
			end if;
			case shift is
				when "100000000" => da(7) <= '1';
				when "010000000" => da(7) <= cmp;
										  da(6) <= '1';
				when "001000000" => da(6) <= cmp;
										  da(5) <= '1';
				when "000100000" => da(5) <= cmp;
										  da(4) <= '1';
				when "000010000" => da(4) <= cmp;
										  da(3) <= '1';
				when "000001000" => da(3) <= cmp;
										  da(2) <= '1';
				when "000000100" => da(2) <= cmp;
										  da(1) <= '1';
				when "000000010" => da(1) <= cmp;
										  da(0) <= '1';
				when "000000001" => da(0) <= cmp;
				when others => null;
			end case;
		end if;			
	end process;
	
	Px:process(clk)
	begin
		if rising_edge(clk) then
			da1 <= da;
		end if;
	end process;
	
	P30:process(scanclk, da, eoc)
	begin
		if rising_edge(scanclk) then
			if eoc = '0' then
				tempdata <= "00000000";
				bcd1 <= "0000";
				en <= '0';
				elsif tempdata < da then
					tempdata <= tempdata + 1;
					if bcd1 = "1000" then
						bcd1 <= "0000";
						c1 <= '1';
					else
						bcd1 <= bcd1 + 2;
						c1 <= '0';
					end if;
				elsif tempdata = da then
					en <= '1';
			end if;
		end if;
	end process;
	
	P31:process(c1, eoc)
	begin
		if eoc = '0' then
			bcd2 <= "0000";
			elsif rising_edge(c1) then
				if bcd2 = "1000" then
					bcd2 <= "0000";
					c2 <= '1';
				else
					bcd2 <= bcd2 + 2;
					c2 <= '0';
				end if;
		end if;
	end process;
	
	P32:process(c2, eoc)
	begin
		if eoc = '0' then
			bcd3 <= "0000";
			elsif rising_edge(c2) then
				if bcd3 = "1000" then
					bcd3 <= "0000";
				else
					bcd3 <= bcd3 + 1;
				end if;
		end if;
	end process;
	
	P4:process(clk, en)
	begin
		if rising_edge(clk) then
			if en = '1' then
				bcd11 <= bcd1;
				bcd12 <= bcd2;
				bcd13 <= bcd3;
				start <= '1';
			else 
				start <= '0';
			end if;
		end if;
	end process;
	
	P5:process(scanclk)
	begin
		if rising_edge(scanclk) then
			if row >= "010" then
				row <= "010";
			else
				row <= row + 1;
			end if;
		end if;
	end process;
	
	P6:process(row)
	begin
		case row is
			when "000" => bcd <= bcd13;
							  led8 <= '1';
			when "001" => bcd <= bcd12;
							  led8 <= '0';
			when "010" => bcd <= bcd11;
							  led8 <= '0';
			when others => null;
		end case;
	end process;
	
	with bcd select
	led <= "0110000" when "0001",		--1
			 "1101101" when "0010",		--2
			 "1111001" when "0011",		--3
			 "0110011" when "0100",		--4
			 "1011011" when "0101",		--5
			 "1011111" when "0110",		--6
			 "1110000" when "0111",		--7
			 "1111111" when "1000",		--8
			 "1111011" when "1001",		--9
			 "1111110" when others;		--0

end Behavioral;