mw_c28xx_csl.c

由MATLAB生成的RTDX的源代码

#include "DSP281x_Device.h"
#include "rtwtypes.h"
#include "c2812rtdxtest.h"
#include "c2812rtdxtest_private.h"

extern interrupt void datalog_isr (void);

volatile int pendingInterrupt = 0;

/* Function: schedulerTimer_ISR() -------------------------------------
 *
 * Abstract:
 *      This function services interrupts posted by scheduler timer
 */

interrupt void schedulerTimer_ISR(void)
{
  pendingInterrupt = 1;
  PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Enable CPU INT1 - hooked to CPU Timer 0
}

/*-----------------------------------------------------------------------------
 * void config_schedulerTimer(void)
 *
 * Abstract:
 *      This function configures scheduler timer
 */

void config_schedulerTimer(void)
{
  InitCpuTimers();

  /* Reassign the PIE vector for TINT0 to point to a specific ISR */
  EALLOW;
  PieVectTable.TINT0 = &schedulerTimer_ISR;
  EDIS;

  /* Configure CPU-Timer 0 to interrupt every 0.1 sec. */
  /* Parameters:  Timer Pointer, CPU Freq in MHz, Period in usec. */
  ConfigCpuTimer(&CpuTimer0, 150, 0.1 * 1000000);
  StartCpuTimer0();

  /* Enable TINT0 in the PIE: Group 1 interrupt 7 */
  PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
}

void disableWatchdog(void)
{
  int *WatchdogWDCR = (void *) 0x7029;
  asm(" EALLOW ");
  *WatchdogWDCR = 0x0068;
  asm(" EDIS ");
}

/* Function: enable_interrupts -------------------------------
 *
 * Abstract:
 *      Enable required c2800 DSP interrupts
 */

void enable_interrupts()
{
  EALLOW;
  PieVectTable.DATALOG = &datalog_isr; // Hook RTDX interrupt to the default ISR
  EDIS;
  IER |= M_DLOG;                        // Enable CPU DLOG interrupt:
  PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Enable CPU INT1 - hooked to CPU Timer 0
  IER |= M_INT1;                        // Enable Global INT1 (CPU Interrupt 1)
  EINT;                                 // Enable Global interrupt INTM
}

/* Function: disable_interrupts -------------------------------
 *
 * Abstract:
 *      Disable required c2800 DSP interrupts
 */

void disable_interrupts()
{
  IER &= M_INT1;                        // Disable Global INT1 (CPU Interrupt 1)
  DINT;                                 // Disable Global interrupt INTM
}

/* Function: init_board() -------------------------------------
 *
 * Abstract:
 *      This function initializes the board
 */

void init_board ()
{
  InitSysCtrl();
  /* Perform additional configuration of the XTINF for speed up */
  XintfRegs.XINTCNF2.bit.XTIMCLK = 0;   // XTIMCLK=SYSCLKOUT/1
  XintfRegs.XINTCNF2.bit.CLKOFF = 0;    // XCLKOUT is enabled
  XintfRegs.XINTCNF2.bit.CLKMODE = 0;   // XCLKOUT = XTIMCLK

  // Make sure write buffer is empty before configuring buffering depth
  while(XintfRegs.XINTCNF2.bit.WLEVEL != 0); // poll the WLEVEL bit
  XintfRegs.XINTCNF2.bit.WRBUFF = 0;    // No write buffering

  // Example: Assume Zone 7 is slow, so add additional BCYC cycles whenever
  // switching from Zone 7 to another Zone.  This will help avoid bus contention.
  XintfRegs.XBANK.bit.BCYC = 7;         // Add 7 cycles
  XintfRegs.XBANK.bit.BANK = 7;         // select zone 7

  /* Zone 0 Configuration */
  XintfRegs.XTIMING0.bit.X2TIMING = 0; // Timing scale factor = 1
  XintfRegs.XTIMING0.bit.XSIZE = 3;     // Always write as 11b
  XintfRegs.XTIMING0.bit.READYMODE = 1; // XREADY is asynchronous
  XintfRegs.XTIMING0.bit.USEREADY = 0; // Disable XREADY
  XintfRegs.XTIMING0.bit.XRDLEAD = 1;   // Read lead time
  XintfRegs.XTIMING0.bit.XRDACTIVE = 2; // Read active time
  XintfRegs.XTIMING0.bit.XRDTRAIL = 0; // Read trail time
  XintfRegs.XTIMING0.bit.XWRLEAD = 1;   // Write lead time
  XintfRegs.XTIMING0.bit.XWRACTIVE = 2; // Write active time
  XintfRegs.XTIMING0.bit.XWRTRAIL = 0; // Write trail time

  /* Zone 1 Configuration */
  XintfRegs.XTIMING1.bit.X2TIMING = 0; // Timing scale factor = 1
  XintfRegs.XTIMING1.bit.XSIZE = 3;     // Always write as 11b
  XintfRegs.XTIMING1.bit.READYMODE = 1; // XREADY is asynchronous
  XintfRegs.XTIMING1.bit.USEREADY = 0; // Disable XREADY
  XintfRegs.XTIMING1.bit.XRDLEAD = 1;   // Read lead time
  XintfRegs.XTIMING1.bit.XRDACTIVE = 2; // Read active time
  XintfRegs.XTIMING1.bit.XRDTRAIL = 0; // Read trail time
  XintfRegs.XTIMING1.bit.XWRLEAD = 1;   // Write lead time
  XintfRegs.XTIMING1.bit.XWRACTIVE = 2; // Write active time
  XintfRegs.XTIMING1.bit.XWRTRAIL = 0; // Write trail time

  /* Zone 2 Configuration */
  XintfRegs.XTIMING2.bit.X2TIMING = 0; // Timing scale factor = 1
  XintfRegs.XTIMING2.bit.XSIZE = 3;     // Always write as 11b
  XintfRegs.XTIMING2.bit.READYMODE = 1; // XREADY is asynchronous
  XintfRegs.XTIMING2.bit.USEREADY = 0; // Disable XREADY
  XintfRegs.XTIMING2.bit.XRDLEAD = 1;   // Read lead time
  XintfRegs.XTIMING2.bit.XRDACTIVE = 2; // Read active time
  XintfRegs.XTIMING2.bit.XRDTRAIL = 0; // Read trail time
  XintfRegs.XTIMING2.bit.XWRLEAD = 1;   // Write lead time
  XintfRegs.XTIMING2.bit.XWRACTIVE = 2; // Write active time
  XintfRegs.XTIMING2.bit.XWRTRAIL = 0; // Write trail time

  /* Zone 6 Configuration */
  XintfRegs.XTIMING6.bit.X2TIMING = 0; // Timing scale factor = 1
  XintfRegs.XTIMING6.bit.XSIZE = 3;     // Always write as 11b
  XintfRegs.XTIMING6.bit.READYMODE = 1; // XREADY is asynchronous
  XintfRegs.XTIMING6.bit.USEREADY = 0; // Disable XREADY
  XintfRegs.XTIMING6.bit.XRDLEAD = 1;   // Read lead time
  XintfRegs.XTIMING6.bit.XRDACTIVE = 2; // Read active time
  XintfRegs.XTIMING6.bit.XRDTRAIL = 0; // Read trail time
  XintfRegs.XTIMING6.bit.XWRLEAD = 1;   // Write lead time
  XintfRegs.XTIMING6.bit.XWRACTIVE = 2; // Write active time
  XintfRegs.XTIMING6.bit.XWRTRAIL = 0; // Write trail time

  /* Zone 7 Configuration */
  XintfRegs.XTIMING7.bit.X2TIMING = 0; // Timing scale factor = 1
  XintfRegs.XTIMING7.bit.XSIZE = 3;     // Always write as 11b
  XintfRegs.XTIMING7.bit.READYMODE = 1; // XREADY is asynchronous
  XintfRegs.XTIMING7.bit.USEREADY = 0; // Disable XREADY
  XintfRegs.XTIMING7.bit.XRDLEAD = 1;   // Read lead time
  XintfRegs.XTIMING7.bit.XRDACTIVE = 2; // Read active time
  XintfRegs.XTIMING7.bit.XRDTRAIL = 0; // Read trail time
  XintfRegs.XTIMING7.bit.XWRLEAD = 1;   // Write lead time
  XintfRegs.XTIMING7.bit.XWRACTIVE = 2; // Write active time
  XintfRegs.XTIMING7.bit.XWRTRAIL = 0; // Write trail time

  /* Flush pipeline to ensure that the write is complete. Wait to be sure. */
  asm(" RPT #6 || NOP");

  /* Disable and clear all CPU interrupts */
  DINT;
  IER = 0x0000;
  IFR = 0x0000;

  InitPieCtrl();
  InitPieVectTable();

  /* initial SPI function.... */

  /* initial SCI function.... */
}