xil_idct_v2_1_0.mpd

一些有用的IP核

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#       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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#       (c) Copyright 2002 Xilinx Inc.
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##
## Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
##
## xil_idct_v2_0_0.mpd
##
## Microprocessor Peripheral Definition
##
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BEGIN xil_idct, IPTYPE=PERIPHERAL, HDL=VHDL, EDIF=TRUE

# Define bus interface
BUS_INTERFACE BUS=SFSL, BUS_STD=FSL, BUS_TYPE=SLAVE
BUS_INTERFACE BUS=MFSL, BUS_STD=FSL, BUS_TYPE=MASTER

# Global ports
PORT Clk   = "", DIR=IN, SIGIS=CLK
# rosinger EDK 6.2i PORT Reset = "", DIR=IN, BUS = MFSL0:SFSL0
PORT Reset = "", DIR=IN , BUS = MFSL:SFSL

## proware signals
PORT FSL_S_CLK     = FSL_S_Clk,     DIR=out, SIGIS=CLOCK, BUS=SFSL, 
PORT FSL_S_READ    = FSL_S_Read,    DIR=out, BUS=SFSL
PORT FSL_S_DATA    = FSL_S_Data,    DIR=in, VEC=[0:31], BUS=SFSL
PORT FSL_S_CONTROL = FSL_S_Control, DIR=in,BUS=SFSL
PORT FSL_S_EXISTS  = FSL_S_Exists,  DIR=in, BUS=SFSL

PORT FSL_M_CLK     = FSL_M_Clk,     DIR=out, SIGIS=CLOCK, BUS=MFSL
PORT FSL_M_WRITE   = FSL_M_Write,   DIR=out, BUS=MFSL
PORT FSL_M_DATA    = FSL_M_Data,    DIR=out, VEC=[0:31], BUS=MFSL
PORT FSL_M_CONTROL = FSL_M_Control, DIR=out, BUS=MFSL
PORT FSL_M_FULL    = FSL_M_Full,    DIR=in, BUS=MFSL

END