bram_block_1_elaborate.vhd

一些有用的IP核

LIBRARY unisim;
USE unisim.vcomponents.ALL;

--------------------------------------------------------------------------------
-- bram_block_1_elaborate.vhd
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- synthesis translate_off
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
-- synthesis translate_on

ENTITY bram_block_1_elaborate IS
GENERIC (
	C_MEMSIZE : INTEGER := 8192;
	C_PORT_DWIDTH : INTEGER := 32;
	C_PORT_AWIDTH : INTEGER := 32;
	C_NUM_WE : INTEGER := 4;
	C_FAMILY : STRING := "virtex2");
PORT (
	-- instance GLOBAL
	BRAM_Addr_B : IN STD_LOGIC_VECTOR(0 TO 31);
	BRAM_EN_A : IN STD_LOGIC;
	BRAM_Dout_A : IN STD_LOGIC_VECTOR(0 TO 31);
	BRAM_EN_B : IN STD_LOGIC;
	BRAM_Dout_B : IN STD_LOGIC_VECTOR(0 TO 31);
	BRAM_Din_A : OUT STD_LOGIC_VECTOR(0 TO 31);
	BRAM_Din_B : OUT STD_LOGIC_VECTOR(0 TO 31);
	BRAM_WEN_A : IN STD_LOGIC_VECTOR(0 TO 3);
	BRAM_Clk_A : IN STD_LOGIC;
	BRAM_WEN_B : IN STD_LOGIC_VECTOR(0 TO 3);
	BRAM_Clk_B : IN STD_LOGIC;
	BRAM_Rst_A : IN STD_LOGIC;
	BRAM_Rst_B : IN STD_LOGIC;
	BRAM_Addr_A : IN STD_LOGIC_VECTOR(0 TO 31));
END bram_block_1_elaborate;

ARCHITECTURE IMP OF bram_block_1_elaborate IS

--------------------------------------------------------------------------------
COMPONENT RAMB16_S9_S9 IS
PORT (
	DIA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	DIB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	DOPA : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
	DOPB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
	CLKA : IN STD_LOGIC;
	CLKB : IN STD_LOGIC;
	ADDRA : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	DOA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	DOB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	ENA : IN STD_LOGIC;
	SSRA : IN STD_LOGIC;
	ENB : IN STD_LOGIC;
	DIPA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
	SSRB : IN STD_LOGIC;
	DIPB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
	WEA : IN STD_LOGIC;
	WEB : IN STD_LOGIC);
END COMPONENT;

--------------------------------------------------------------------------------
-- internal signals
--------------------------------------------------------------------------------

	SIGNAL dina : STD_LOGIC_VECTOR(31 DOWNTO 0);

	SIGNAL dinb : STD_LOGIC_VECTOR(31 DOWNTO 0);

	SIGNAL douta : STD_LOGIC_VECTOR(31 DOWNTO 0);

	SIGNAL doutb : STD_LOGIC_VECTOR(31 DOWNTO 0);

	SIGNAL net_gnd0 : STD_LOGIC;

	SIGNAL net_gnd1 : STD_LOGIC_VECTOR(0 TO 0);

BEGIN

--------------------------------------------------------------------------------
-- Power assignments
net_gnd0 <= '0';
net_gnd1 <= "0";
--------------------------------------------------------------------------------
-- Constant assignments
--------------------------------------------------------------------------------
-- Top-level port assignments
dina <= BRAM_Dout_A;
dinb <= BRAM_Dout_B;
BRAM_Din_A <= douta;
BRAM_Din_B <= doutb;
--------------------------------------------------------------------------------
-- Lower-level assignments

--------------------------------------------------------------------------------
ramb16_s9_s9_0 : RAMB16_S9_S9
PORT MAP (
	DIA => dina(31 DOWNTO 24),
	DIB => dinb(31 DOWNTO 24),
	DOPA => open,
	DOPB => open,
	CLKA => BRAM_Clk_A,
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(19 TO 29),
	ADDRB => BRAM_Addr_B(19 TO 29),
	DOA => douta(31 DOWNTO 24),
	DOB => doutb(31 DOWNTO 24),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	DIPA => net_gnd1,
	SSRB => net_gnd0,
	DIPB => net_gnd1,
	WEA => BRAM_WEN_A(0),
	WEB => BRAM_WEN_B(0));

--------------------------------------------------------------------------------
ramb16_s9_s9_1 : RAMB16_S9_S9
PORT MAP (
	DIA => dina(23 DOWNTO 16),
	DIB => dinb(23 DOWNTO 16),
	DOPA => open,
	DOPB => open,
	CLKA => BRAM_Clk_A,
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(19 TO 29),
	ADDRB => BRAM_Addr_B(19 TO 29),
	DOA => douta(23 DOWNTO 16),
	DOB => doutb(23 DOWNTO 16),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	DIPA => net_gnd1,
	SSRB => net_gnd0,
	DIPB => net_gnd1,
	WEA => BRAM_WEN_A(1),
	WEB => BRAM_WEN_B(1));

--------------------------------------------------------------------------------
ramb16_s9_s9_2 : RAMB16_S9_S9
PORT MAP (
	DIA => dina(15 DOWNTO 8),
	DIB => dinb(15 DOWNTO 8),
	DOPA => open,
	DOPB => open,
	CLKA => BRAM_Clk_A,
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(19 TO 29),
	ADDRB => BRAM_Addr_B(19 TO 29),
	DOA => douta(15 DOWNTO 8),
	DOB => doutb(15 DOWNTO 8),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	DIPA => net_gnd1,
	SSRB => net_gnd0,
	DIPB => net_gnd1,
	WEA => BRAM_WEN_A(2),
	WEB => BRAM_WEN_B(2));

--------------------------------------------------------------------------------
ramb16_s9_s9_3 : RAMB16_S9_S9
PORT MAP (
	DIA => dina(7 DOWNTO 0),
	DIB => dinb(7 DOWNTO 0),
	DOPA => open,
	DOPB => open,
	CLKA => BRAM_Clk_A,
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(19 TO 29),
	ADDRB => BRAM_Addr_B(19 TO 29),
	DOA => douta(7 DOWNTO 0),
	DOB => doutb(7 DOWNTO 0),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	DIPA => net_gnd1,
	SSRB => net_gnd0,
	DIPB => net_gnd1,
	WEA => BRAM_WEN_A(3),
	WEB => BRAM_WEN_B(3));

END ARCHITECTURE IMP;