idct.vhd

一些有用的IP核

-------------------------------------------------------------------------------
--
--       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
--       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
--       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
--       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
--       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
--       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
--       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
--       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
--       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
--       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
--       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
--       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--       FOR A PARTICULAR PURPOSE.
--
--       (c) Copyright 2002 Xilinx Inc.
--       All rights reserved.
--
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library unisim;
use unisim.all;

entity iDCT is
  port (
    Clk            : in  std_logic;
    Reset          : in  std_logic;
    Data_In        : in  std_logic_vector(15 downto 0);
    Data_In_Valid  : in  std_logic;
    Read_Data_In   : out std_logic;
    Data_Out_Full  : in  std_logic;
    Data_Out       : out std_logic_vector(31 downto 0);
    Data_Out_Valid : out std_logic);  
end entity iDCT;



architecture IMP of iDCT is

  component FDE is
    port (
      Q  : out std_logic;
      C  : in  std_logic;
      CE : in  std_logic;
      D  : in  std_logic);
  end component FDE;


  component RAM16x1S is
    port (
      WE   : in  std_logic;
      D    : in  std_logic;
      WClk : in  std_logic;
      A0   : in  std_logic;
      A1   : in  std_logic;
      A2   : in  std_logic;
      A3   : in  std_logic;
      O    : out std_logic);
  end component RAM16x1S;

  component MULT18x18S is
    port (
      A  : in  std_logic_vector(17 downto 0);
      B  : in  std_logic_vector(17 downto 0);
      C  : in  std_logic;
      CE : in  std_logic;
      R  : in  std_logic;
      P  : out std_logic_vector(35 downto 0));
  end component MULT18x18S;
  
  subtype COEFF_TYPE is signed(15 downto 0);
  type    COEFF_ARRAY_TYPE is array (natural range 0 to 7) of COEFF_TYPE;
  type    COEFF_MATRIX_TYPE is array (natural range 0 to 7) of COEFF_ARRAY_TYPE;

  constant Coeff_T : COEFF_MATRIX_TYPE := (
    0 => (
      to_signed(16384, COEFF_TYPE'length),
      to_signed(22725, COEFF_TYPE'length),
      to_signed(21407, COEFF_TYPE'length),
      to_signed(19266, COEFF_TYPE'length),
      to_signed(16384, COEFF_TYPE'length),
      to_signed(12873, COEFF_TYPE'length),
      to_signed(8867, COEFF_TYPE'length),
      to_signed(4520, COEFF_TYPE'length)
      ),
    1 => (
      to_signed(16384, COEFF_TYPE'length),
      to_signed(19266, COEFF_TYPE'length),
      to_signed(8867, COEFF_TYPE'length),
      to_signed(-4521, COEFF_TYPE'length),
      to_signed(-16384, COEFF_TYPE'length),
      to_signed(-22726, COEFF_TYPE'length),
      to_signed(-21407, COEFF_TYPE'length),
      to_signed(-12873, COEFF_TYPE'length)
      ),
    2 => (
      to_signed(16384, COEFF_TYPE'length),
      to_signed(12873, COEFF_TYPE'length),
      to_signed(-8867, COEFF_TYPE'length),
      to_signed(-22726, COEFF_TYPE'length),
      to_signed(-16385, COEFF_TYPE'length),
      to_signed(4520, COEFF_TYPE'length),
      to_signed(21407, COEFF_TYPE'length),
      to_signed(19266, COEFF_TYPE'length)
      ),
    3 => (
      to_signed(16384, COEFF_TYPE'length),
      to_signed(4520, COEFF_TYPE'length),
      to_signed(-21407, COEFF_TYPE'length),
      to_signed(-12873, COEFF_TYPE'length),
      to_signed(16384, COEFF_TYPE'length),
      to_signed(19266, COEFF_TYPE'length),
      to_signed(-8867, COEFF_TYPE'length),
      to_signed(-22726, COEFF_TYPE'length)
      ),
    4 => (
      to_signed(16384, COEFF_TYPE'length),
      to_signed(-4521, COEFF_TYPE'length),
      to_signed(-21407, COEFF_TYPE'length),
      to_signed(12873, COEFF_TYPE'length),
      to_signed(16384, COEFF_TYPE'length),
      to_signed(-19266, COEFF_TYPE'length),
      to_signed(-8867, COEFF_TYPE'length),
      to_signed(22725, COEFF_TYPE'length)
      ),
    5 => (
      to_signed(16384, COEFF_TYPE'length),
      to_signed(-12873, COEFF_TYPE'length),
      to_signed(-8867, COEFF_TYPE'length),
      to_signed(22725, COEFF_TYPE'length),
      to_signed(-16384, COEFF_TYPE'length),
      to_signed(-4521, COEFF_TYPE'length),
      to_signed(21407, COEFF_TYPE'length),
      to_signed(-19266, COEFF_TYPE'length)
      ),
    6 => (
      to_signed(16384, COEFF_TYPE'length),
      to_signed(-19266, COEFF_TYPE'length),
      to_signed(8867, COEFF_TYPE'length),
      to_signed(4520, COEFF_TYPE'length),
      to_signed(-16385, COEFF_TYPE'length),
      to_signed(22725, COEFF_TYPE'length),
      to_signed(-21407, COEFF_TYPE'length),
      to_signed(12873, COEFF_TYPE'length)
      ),
    7 => (
      to_signed(16384, COEFF_TYPE'length),
      to_signed(-22726, COEFF_TYPE'length),
      to_signed(21407, COEFF_TYPE'length),
      to_signed(-19266, COEFF_TYPE'length),
      to_signed(16384, COEFF_TYPE'length),
      to_signed(-12873, COEFF_TYPE'length),
      to_signed(8867, COEFF_TYPE'length),
      to_signed(-4521, COEFF_TYPE'length)
      )
    );

  signal move_pipeline     : std_logic;
  signal move_in_pipeline  : std_logic;
  signal move_out_pipeline : std_logic;

  signal Index         : natural range 0 to 7;
  signal Index_1       : natural range 0 to 7;
  signal Index_2       : natural range 0 to 7;
  signal Word          : natural range 0 to 7;
  signal Word_1        : natural range 0 to 7;
  signal First_Cycle   : std_logic;
  signal First_Cycle_1 : std_logic;
  signal Last_Cycle    : std_logic;

  subtype MAC_RESULT_TYPE is std_logic_vector(31 downto 0);

  signal MAC_Result          : MAC_RESULT_TYPE;
  signal New_MAC_Result      : MAC_RESULT_TYPE;
--  signal Wr_New_MAC_Result_i : std_logic;
  signal Wr_New_MAC_Result   : std_logic;
  signal Wr_New_MAC_Result_1 : std_logic;
  signal Wr_New_MAC_Result_2 : std_logic;

  signal Writing_Result   : std_logic;
  signal Writing_Result_i : std_logic;

  signal mul_op_a : std_logic_vector(Data_In'range);
  signal mul_op_b : COEFF_TYPE;
  
  signal mult_op_a : std_logic_vector(17 downto 0);
  signal mult_op_b : std_logic_vector(17 downto 0);
  signal mult_res  : std_logic_vector(35 downto 0);
  signal mult_en   : std_logic;