xil_idct_v2_1_0.mpd

一些有用的IP核

###############################################################################
#
#       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
#       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
#       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
#       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
#       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
#       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
#       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
#       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
#       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
#       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
#       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
#       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
#       FOR A PARTICULAR PURPOSE.
#
#       (c) Copyright 2002 Xilinx Inc.
#       All rights reserved.
#
##############################################################################
################################################################################
##
## Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
##
## xil_idct_v2_0_0.mpd
##
## Microprocessor Peripheral Definition
##
################################################################################

PARAMETER VERSION = 2.0.0

BEGIN xil_idct, IPTYPE=PERIPHERAL, HDL=VHDL, EDIF=TRUE

# Define bus interface
BUS_INTERFACE BUS=SFSL0, BUS_STD=FSL, BUS_TYPE=SLAVE
BUS_INTERFACE BUS=MFSL0, BUS_STD=FSL, BUS_TYPE=MASTER
BUS_INTERFACE BUS=SFSL1, BUS_STD=FSL, BUS_TYPE=SLAVE
BUS_INTERFACE BUS=MFSL1, BUS_STD=FSL, BUS_TYPE=MASTER

# Generics for vhdl or parameters for verilog
PARAMETER C_DWIDTH = 32, DT=integer

# Global ports
PORT Clk = "", DIR=IN, SIGIS=CLK, BUS = SOPB
PORT Reset = OPB_Rst, DIR=IN, BUS = MFSL0:SFSL0:MFSL1:SFSL1

## proware signals
PORT FSL0_S_CLK = FSL_S_Clk, DIR=out, SIGIS=CLOCK, BUS=SFSL0, 
PORT FSL0_S_READ = FSL_S_Read, DIR=out, BUS=SFSL0
PORT FSL0_S_DATA = FSL_S_Data, DIR=in, VEC=[0:C_DWIDTH-1], BUS=SFSL0
PORT FSL0_S_CONTROL = FSL_S_Control, DIR=in,BUS=SFSL0
PORT FSL0_S_EXISTS = FSL_S_Exists, DIR=in, BUS=SFSL0
PORT FSL0_M_CLK = FSL_M_Clk, DIR=out, SIGIS=CLOCK, BUS=MFSL0
PORT FSL0_M_WRITE = FSL_M_Write, DIR=out, BUS=MFSL0
PORT FSL0_M_DATA = FSL_M_Data, DIR=out, VEC=[0:C_DWIDTH-1], BUS=MFSL0
PORT FSL0_M_CONTROL = FSL_M_Control, DIR=out, BUS=MFSL0
PORT FSL0_M_FULL = FSL_M_Full, DIR=in, BUS=MFSL0


PORT FSL1_S_CLK = FSL_S_Clk, DIR=out, SIGIS=CLOCK, BUS=SFSL1, 
PORT FSL1_S_READ = FSL_S_Read, DIR=out, BUS=SFSL1
PORT FSL1_S_DATA = FSL_S_Data, DIR=in, VEC=[0:C_DWIDTH-1], BUS=SFSL1
PORT FSL1_S_CONTROL = FSL_S_Control, DIR=in,BUS=SFSL1
PORT FSL1_S_EXISTS = FSL_S_Exists, DIR=in, BUS=SFSL1
PORT FSL1_M_CLK = FSL_M_Clk, DIR=out, SIGIS=CLOCK, BUS=MFSL1
PORT FSL1_M_WRITE = FSL_M_Write, DIR=out, BUS=MFSL1
PORT FSL1_M_DATA = FSL_M_Data, DIR=out, VEC=[0:C_DWIDTH-1], BUS=MFSL1
PORT FSL1_M_CONTROL = FSL_M_Control, DIR=out, BUS=MFSL1
PORT FSL1_M_FULL = FSL_M_Full, DIR=in, BUS=MFSL1

END