usbdl_usb_drv.c

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#elif defined(DRV_USB_IP_V2)

	kal_uint8	epctl_value = 0;


	/* check the packet size, FIFO only 8 bytes*/
	if((epno == 0)||((epno == 3)&&(data_size != 8)))
		EXT_ASSERT(0, epno, 0, 0);

	switch(type)
	{
	case USB_ENDPT_BULK:
		epctl_value = VUSB_ENDPT_BULK_RX;
		break;
	case USB_ENDPT_INTR:
		epctl_value = VUSB_ENDPT_BULK_RX;
		break;
	/* not support */
	case USB_ENDPT_CTRL:
	case USB_ENDPT_ISO:
		ASSERT(0);
		break;
	}

	g_UsbDrvInfo.ep_out_max_data_size[epno-1] =  (kal_uint8)data_size;
	
	DRV_WriteReg8(USB_ENDPT_CTL(epno), DRV_Reg8(USB_ENDPT_CTL(epno))|epctl_value);
	
#elif defined(DRV_USB_IP_V1)
	if(epno == 0)
		ASSERT(0);

	DRV_WriteReg8(USB_INDEX,epno);
	DRV_WriteReg8(USB_OUTCSR1,(USB_OUTCSR1_CLRDATATOG | USB_OUTCSR1_FLUSHFIFO));
	DRV_WriteReg8(USB_OUTMAXP, (kal_uint8)(data_size/8));
#endif
}


void USB_EP0En(void)
{
#if defined(DRV_USB_IP_V3)
	/* default address is from 0 to 63  */
	DRV_WriteReg(USB_INTRTXE, DRV_Reg(USB_INTRTXE)|USB_INTRE_EPEN);
#elif defined(DRV_USB_IP_V2)
	DRV_WriteReg8(USB_ENDPT_CTL(0), VUSB_ENDPT_CONTROL);
#elif defined(DRV_USB_IP_V1)
	DRV_Reg8(USB_INTRIN1E) |= USB_INTRIN1E_EPEN;
#endif
}


void USB_TxEPEn(kal_uint8 epno, kal_bool bDMA, kal_bool is_flush)
{
	if(epno == 0)
		ASSERT(0);

#if defined(DRV_USB_IP_V3)

	DRV_WriteReg8(USB_INDEX, epno);
	/* double buffers, so flush twice  */
	if(is_flush == KAL_TRUE)
	{
		DRV_WriteReg(USB_TXCSR, (USB_TXCSR_FLUSHFIFO|USB_TXCSR_CLRDATATOG));
		DRV_WriteReg(USB_TXCSR, (USB_TXCSR_FLUSHFIFO|USB_TXCSR_CLRDATATOG));
	}
	DRV_Reg(USB_INTRTXE) |= USB_INTRE_EPEN<<epno;
	/* Only configure as multiple packet DMA TX mode */
	DRV_WriteReg(USB_TXCSR, USB_TXCSR_AUTOSET|USB_TXCSR_DMAREQENAB|USB_TXCSR_DMAREQMODE);

#elif defined(DRV_USB_IP_V2)

	if(bDMA == KAL_TRUE)
	{
		g_UsbDrvInfo.ep_in_enb_state[epno-1] = USB_EP_ENB_DMA;
	}	
	else
        {
		g_UsbDrvInfo.ep_in_enb_state[epno-1] = USB_EP_ENB_NORMAL;
	}

#elif defined(DRV_USB_IP_V1)

	DRV_WriteReg8(USB_INDEX, epno);

	if(bDMA == KAL_TRUE)
	{
		DRV_Reg8(USB_INTRIN1E) = DRV_Reg8(USB_INTRIN1E) & (~(USB_INTRIN1E_EPEN << epno));
		if(is_flush == KAL_TRUE)
		{
			DRV_WriteReg8(USB_INCSR1, (USB_INCSR1_CLRDATATOG | USB_INCSR1_FLUSHFIFO));
			DRV_WriteReg8(USB_INCSR1, (USB_INCSR1_CLRDATATOG | USB_INCSR1_FLUSHFIFO));
		}
//		DRV_WriteReg8(USB_INCSR2, 0);
		DRV_WriteReg8(USB_INCSR2, (USB_INCSR2_AUTOSET | USB_INCSR2_DMAENAB));
	}
	else
	{
		if(is_flush == KAL_TRUE)
		{
			DRV_WriteReg8(USB_INCSR1,(USB_INCSR1_CLRDATATOG | USB_INCSR1_FLUSHFIFO));
			DRV_WriteReg8(USB_INCSR1,(USB_INCSR1_CLRDATATOG | USB_INCSR1_FLUSHFIFO));
		}
		DRV_WriteReg8(USB_INCSR2,0);
		DRV_Reg8(USB_INTRIN1E) |= (USB_INTRIN1E_EPEN << epno);
	}
#endif	
}


void USB_TxEPDis(kal_uint8 epno, kal_bool bDMA)
{
	if(epno == 0)
		ASSERT(0);

#if defined(DRV_USB_IP_V3)

	USB_Stop_DMA_Channel(epno, USB_TX_EP_TYPE);
	DRV_Reg(USB_INTRTXE) &= ~(USB_INTRE_EPEN<<epno);
	DRV_WriteReg8(USB_INDEX, epno);
	DRV_WriteReg(USB_TXCSR, (USB_TXCSR_FLUSHFIFO|USB_TXCSR_CLRDATATOG));
	DRV_WriteReg(USB_TXCSR, (USB_TXCSR_FLUSHFIFO|USB_TXCSR_CLRDATATOG));

#elif defined(DRV_USB_IP_V2)
	#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
	#endif
	g_UsbDrvInfo.ep_in_enb_state[epno-1] = USB_EP_DIS;
	WRITE_EPN_BDT_PID(epno, USB_BDT_TX, 0);

#elif defined(DRV_USB_IP_V1)

	DRV_WriteReg8(USB_INDEX, epno);
	
	if(bDMA == KAL_TRUE)
        {
        	#if 0
/* under construction !*/
/* under construction !*/
		#endif
		DRV_Reg8(USB_INTRIN1E) = DRV_Reg8(USB_INTRIN1E) & (~(USB_INTRIN1E_EPEN << epno));
		DRV_WriteReg8(USB_INCSR2,0);
	}
	else
	{
		DRV_Reg8(USB_INTRIN1E) = DRV_Reg8(USB_INTRIN1E) & (~(USB_INTRIN1E_EPEN << epno));
		DRV_WriteReg8(USB_INCSR2,0);
	}
#endif	
}


void USB_RxEPEn(kal_uint8 epno, kal_bool bDMA, kal_bool is_flush)
{
	if(epno == 0)
		ASSERT(0);


#if defined(DRV_USB_IP_V3)

	DRV_WriteReg8(USB_INDEX, epno);

	/* maybe double buffer, so flush twice  */
	if(is_flush == KAL_TRUE)
	{
		DRV_WriteReg(USB_RXCSR, (USB_RXCSR_FLUSHFIFO|USB_RXCSR_CLRDATATOG));
		DRV_WriteReg(USB_RXCSR, (USB_RXCSR_FLUSHFIFO|USB_RXCSR_CLRDATATOG));
	}
	DRV_Reg(USB_INTRRXE) |= USB_INTRE_EPEN<<epno;

#elif defined(DRV_USB_IP_V2)

	if(bDMA == KAL_TRUE)
	{
		g_UsbDrvInfo.ep_out_enb_state[epno-1] = USB_EP_ENB_DMA;
		/* The first expect received packet is data0*/
		g_UsbDrvInfo.ep_out_data01[epno-1] = 0;
	}	
	else
	{
		g_UsbDrvInfo.ep_out_enb_state[epno-1] = USB_EP_ENB_NORMAL;
		/* The first expect received packet is data0*/
		g_UsbDrvInfo.ep_out_data01[epno-1] = 0;
		// configure BDT to receive data
		WRITE_EPN_BDT_PID(epno, USB_BDT_RX, 
			(g_UsbDrvInfo.ep_out_max_data_size[epno-1] << VUSB_BDT_BC_SHIFT) |
			(g_UsbDrvInfo.ep_out_data01[epno-1]<<VUSB_BDT_DATA01_SHIFT) |
			VUSB_BDT_DTS_BIT | VUSB_BDT_OWNS_BIT);
		g_UsbDrvInfo.ep_out_data01[epno-1] ^= 1;
	}

#elif defined(DRV_USB_IP_V1)

	DRV_WriteReg8(USB_INDEX, epno);

	if(bDMA == KAL_TRUE)
	{
		DRV_Reg8(USB_INTROUT1E) = DRV_Reg8(USB_INTROUT1E) & (~(USB_INTROUT1E_EPEN<<epno));
		if(is_flush == KAL_TRUE)
		{
			DRV_WriteReg8(USB_OUTCSR1,(USB_OUTCSR1_CLRDATATOG | USB_OUTCSR1_FLUSHFIFO));
			DRV_WriteReg8(USB_OUTCSR1,(USB_OUTCSR1_CLRDATATOG | USB_OUTCSR1_FLUSHFIFO));
		}
//		DRV_WriteReg8(USB_OUTCSR2,0);
		DRV_WriteReg8(USB_OUTCSR2,(USB_OUTCSR2_AUTOCLEAR | USB_OUTCSR2_DMAENAB));
	}
	else
	{
		if(is_flush == KAL_TRUE)
		{
			DRV_WriteReg8(USB_OUTCSR1,(USB_OUTCSR1_CLRDATATOG | USB_OUTCSR1_FLUSHFIFO));
			DRV_WriteReg8(USB_OUTCSR1,(USB_OUTCSR1_CLRDATATOG | USB_OUTCSR1_FLUSHFIFO));	
		}
		DRV_WriteReg8(USB_OUTCSR2,0);
		DRV_Reg8(USB_INTROUT1E) |= USB_INTROUT1E_EPEN<<epno;
	}
#endif	
}

void USB_RxEPDis(kal_uint8 epno, kal_bool bDMA)
{
	if(epno == 0)
		ASSERT(0);

#if defined(DRV_USB_IP_V3)
	USB_Stop_DMA_Channel(epno, USB_RX_EP_TYPE);
	DRV_Reg(USB_INTRRXE) &= ~(USB_INTRE_EPEN << epno);
	DRV_WriteReg8(USB_INDEX, epno);
	DRV_WriteReg(USB_RXCSR, (USB_RXCSR_FLUSHFIFO|USB_RXCSR_CLRDATATOG));
	DRV_WriteReg(USB_RXCSR, (USB_RXCSR_FLUSHFIFO|USB_RXCSR_CLRDATATOG));
#elif defined(DRV_USB_IP_V2)
	#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
	#endif
	g_UsbDrvInfo.ep_out_enb_state[epno-1] = USB_EP_DIS;
	WRITE_EPN_BDT_PID(epno, USB_BDT_RX, 0);
#elif defined(DRV_USB_IP_V1)

	DRV_WriteReg8(USB_INDEX, epno);
	
	if(bDMA == KAL_TRUE)
	{
		#if 0
/* under construction !*/
/* under construction !*/
		#endif
		DRV_Reg8(USB_INTROUT1E) = DRV_Reg8(USB_INTROUT1E) & (~(USB_INTROUT1E_EPEN << epno));
		DRV_WriteReg8(USB_OUTCSR2, 0);
	}
	else
	{
		DRV_Reg8(USB_INTROUT1E) = DRV_Reg8(USB_INTROUT1E) & (~(USB_INTROUT1E_EPEN << epno));
		DRV_WriteReg8(USB_OUTCSR2, 0);
	}
#endif	
}


void USB_TxEPClearDataTog(kal_uint8 epno)
{
#if defined(DRV_USB_IP_V3)
	DRV_WriteReg8(USB_INDEX, epno);
	DRV_WriteReg(USB_TXCSR, DRV_Reg(USB_TXCSR)|USB_TXCSR_CLRDATATOG);
#elif defined(DRV_USB_IP_V2)

#elif defined(DRV_USB_IP_V1)
	DRV_WriteReg8(USB_INDEX, epno);
	DRV_WriteReg8(USB_INCSR1, DRV_Reg8(USB_INCSR1)|USB_INCSR1_CLRDATATOG);
#endif
}


void USB_RxEPClearDataTog(kal_uint8 epno)
{
#if defined(DRV_USB_IP_V3)
	DRV_WriteReg8(USB_INDEX, epno);
	DRV_WriteReg(USB_RXCSR, DRV_Reg(USB_RXCSR)|USB_RXCSR_CLRDATATOG);
#elif defined(DRV_USB_IP_V2)

#elif defined(DRV_USB_IP_V1)
	DRV_WriteReg8(USB_INDEX, epno);
	DRV_WriteReg8(USB_OUTCSR1, DRV_Reg8(USB_OUTCSR1)|USB_OUTCSR1_CLRDATATOG);
#endif
}


/* Clear EP data01, note that ep0 can not use this function */
void USB_TxEPClearData01(kal_uint8 epno)
{
	if(epno == 0)
		ASSERT(0);
#if defined(DRV_USB_IP_V2)
	g_UsbDrvInfo.ep_in_data01[epno-1] = 0;
#endif	
}

#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#if defined(DRV_USB_IP_V2)
/* under construction !*/
#endif	
/* under construction !*/
#endif

/*  read FIFO data from EP nEP with sfift */
void USB_EPFIFORead_Shift(kal_uint8 nEP, kal_uint16 nBytes, void *pDst, kal_uint32 shift)
{
#if defined(DRV_USB_IP_V1)||defined(DRV_USB_IP_V3)
	kal_uint16  nCount = nBytes;
	kal_uint8   *pby;
	kal_uint32  nAddr;
#endif


	if((nBytes!=0) && (pDst==NULL))
		EXT_ASSERT(0, (kal_uint32)nBytes, 0, 0);
	
#if defined(DRV_USB_IP_V3)
	DRV_WriteReg8(USB_INDEX, nEP);
	nAddr = USB_EP0 + nEP*4;
	pby = (kal_uint8 *)pDst;

	/* read byte by byte */
	while (nCount) 
	{
		*pby++ = DRV_Reg8(nAddr); 
		nCount--;
	}
#elif defined(DRV_USB_IP_V2)
	// make sure this endpoint status belong to MCU
	if(nEP==0)
	{
		if((READ_EP0_BDT_PID(USB_BDT_RX, g_UsbDrvInfo.ep0_rx_even_odd)&VUSB_BDT_OWNS_BIT)!=0)
			ASSERT(0);

		kal_mem_cpy(pDst, (void*)(READ_EP0_BDT_ADDR(USB_BDT_RX, g_UsbDrvInfo.ep0_rx_even_odd) + shift), nBytes);
	}
	else
	{
		ASSERT(g_UsbDrvInfo.ep_out_enb_state[nEP-1] != USB_EP_DIS);
		ASSERT(nBytes <= g_UsbDrvInfo.ep_out_max_data_size[nEP-1]);
		
		if((READ_EPN_BDT_PID(nEP, USB_BDT_RX)&VUSB_BDT_OWNS_BIT)!=0)
			ASSERT(0);

		kal_mem_cpy(pDst, (void*)(READ_EPN_BDT_ADDR(nEP, USB_BDT_RX) + shift), nBytes);
	}
#elif defined(DRV_USB_IP_V1)
	DRV_WriteReg8(USB_INDEX,nEP);
	nAddr = USB_EP0+nEP*4;
	pby = (kal_uint8 *)pDst;

	/* read byte by byte */
	while (nCount) 
	{
		*pby++ = DRV_Reg8(nAddr); 
		nCount--;
	}
#endif	
}


/* Read fifo data from EP nEP*/
void USB_EPFIFORead(kal_uint8 nEP, kal_uint16 nBytes, void *pDst)
{
	USB_EPFIFORead_Shift(nEP, nBytes, pDst, 0);
}


/*  write data to fifo EP nEP*/
void USB_EPFIFOWrite (kal_uint8 nEP, kal_uint16 nBytes, void *pSrc)
{
#if (defined(DRV_USB_IP_V1)||defined(DRV_USB_IP_V3))
	kal_uint16 nCount = nBytes;
	kal_uint8 *pby;
	kal_uint32 nAddr;
#endif

	if((nBytes!=0) && (pSrc==NULL))
		EXT_ASSERT(0, (kal_uint32)nBytes, 0, 0);

#if defined(DRV_USB_IP_V3)
	DRV_WriteReg8(USB_INDEX, nEP);
	nAddr = USB_EP0 + nEP*4;
	pby = (kal_uint8 *)pSrc;

	/* write byte by byte */
	while (nCount) 
	{
		DRV_WriteReg8(nAddr, *pby++);
		nCount--;
	}
#elif defined(DRV_USB_IP_V2)
	if(nEP==0)
	{
		// make sure this endpoint status belong to MCU
		if((READ_EP0_BDT_PID(USB_BDT_TX, g_UsbDrvInfo.ep0_tx_even_odd)&VUSB_BDT_OWNS_BIT)!=0)
			ASSERT(0);
		kal_mem_cpy((void*)READ_EP0_BDT_ADDR(USB_BDT_TX, g_UsbDrvInfo.ep0_tx_even_odd),
					pSrc, nBytes);
		WRITE_EP0_BDT_PID(USB_BDT_TX, g_UsbDrvInfo.ep0_tx_even_odd, nBytes<<VUSB_BDT_BC_SHIFT);
	}
	else
	{
		ASSERT(g_UsbDrvInfo.ep_in_enb_state[nEP-1]!=USB_EP_DIS);
		ASSERT(nBytes<=g_UsbDrvInfo.ep_in_max_data_size[nEP-1]);
		
		// make sure this endpoint status belong to MCU
		if((READ_EPN_BDT_PID(nEP, USB_BDT_TX)&VUSB_BDT_OWNS_BIT)!=0)
			ASSERT(0);
		kal_mem_cpy((void*)READ_EPN_BDT_ADDR(nEP, USB_BDT_TX), pSrc, nBytes);
		WRITE_EPN_BDT_PID(nEP, USB_BDT_TX, nBytes<<VUSB_BDT_BC_SHIFT);
	}
#elif defined(DRV_USB_IP_V1)
	DRV_WriteReg8(USB_INDEX,nEP);
	nAddr = USB_EP0+nEP*4;
	pby = (kal_uint8 *)pSrc;

	/* write by byte */
	while (nCount) 
	{
		DRV_WriteReg8(nAddr,*pby++);
		nCount--;
	}
#endif	
}


/* type == USB_TX_EP_TYPE or USB_RX_EP_TYPE 
    en == KAL_TRUE means stall this endpoint */
void USB_CtrlEPStall(kal_uint8 EPno, USB_EP_TYPE direction, kal_bool en, USB_CTRL_STALL_ENTRY entry)
{
#if defined(DRV_USB_IP_V3)
	kal_uint16  CSR;
#elif defined(DRV_USB_IP_V1)
	kal_uint8 CSR1;
#endif

	if((EPno==0)||(EPno>MAX_INTR_EP_NUM))
		EXT_ASSERT(0, (kal_uint32)EPno, (kal_uint32)entry, 0);

#if defined(DRV_USB_IP_V3)
	if (en == KAL_TRUE)
	{
		/* stall endpoint */
		if(direction == USB_RX_EP_TYPE)
		{
			DRV_WriteReg8(USB_INDEX,  EPno);
			CSR = DRV_Reg(USB_RXCSR);
			DRV_WriteReg(USB_RXCSR, (CSR|USB_RXCSR_FLUSHFIFO|USB_RXCSR_CLRDATATOG|USB_RXCSR_SENDSTALL));
			g_UsbDrvInfo.ep_rx_stall_status[EPno-1] = KAL_TRUE;
		}
		else
		{
			DRV_WriteReg8(USB_INDEX, EPno);
			CSR = DRV_Reg(USB_TXCSR);
			DRV_WriteReg(USB_TXCSR, (CSR|USB_TXCSR_FLUSHFIFO|USB_TXCSR_CLRDATATOG|USB_TXCSR_SENDSTALL));
			g_UsbDrvInfo.ep_tx_stall_status[EPno-1] = KAL_TRUE;
		}
	}
	else
	{
		/* clear stall */
		if (direction == USB_RX_EP_TYPE)
12345

usbdl_usb_drv.c - 源码说明

本页面展示了「MTK 平台启动源码」中的 usbdl_usb_drv.c 源码文件，采用 C语言 编程语言编写，共 2,365 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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