ulaw_8_14.vhd

使用VHDL语言

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ulaw_8_14 is
		PORT(
			data			:in			std_logic_vector(7 downto 0);	--pcm signal a
			frame			:in			std_logic;						--frame synchronous signal
			dataq			:out		std_logic_vector(13 downto 0));	--output overlap signal
end ulaw_8_14;

architecture rtl of ulaw_8_14 is
	signal	data_in			:std_logic_vector(12 downto 0);
	signal	data_sum			:std_logic_vector(12 downto 0);
--	signal	data_buf			:std_logic_vector(7 downto 0);
	constant data_c			:std_logic_vector(12 downto 0) := "1111111011111";	--33'complementary code 
begin
	
	with data(6 downto 4) select
		data_in <= "00000001" & data(3 downto 0) & '1'		when "000",
				   "0000001" & data(3 downto 0) & "10"		when "001",
				   "000001" & data(3 downto 0) & "100"		when "010",
				   "00001" & data(3 downto 0) & "1000"		when "011",
				   "0001" & data(3 downto 0) & "10000"		when "100",
				   "001" & data(3 downto 0) & "100000"		when "101",
				   "01" & data(3 downto 0) & "1000000"		when "110",
				   '1' & data(3 downto 0) & "10000000"		when others;

	data_sum <= data_in + data_c;

	process(frame)
	begin
		if frame'event and frame = '1' then
			dataq <= data(7) & data_sum;
		end if;
	end process;
end rtl;