alaw_3.vhd

使用VHDL实现通信脉冲编码调制（PCM）中的a律转换

library ieee;
use ieee.std_logic_1164.all;

entity alaw_3 is
	port(
		rdata 		: in std_logic_vector(1 downto 0);
      rclock 		: in std_logic_vector(1 downto 0);
      rframe 		: in std_logic_vector(1 downto 0);
      tdata 		: out std_logic_vector(1 downto 0);
      tclock 		: in std_logic_vector(1 downto 0);
      tframe 		: in std_logic_vector(1 downto 0);
      tdata_loc 	: in std_logic;
      rdata_loc	: out std_logic;
		frame_loc	: in std_logic;
		clock_loc	: in std_logic;
		ebi			: in std_logic							--enable even bit(a-law) inversion.1:inverted;0:not inverted           rdata_loc 	: out std_logic;
		);		
end alaw_3;

architecture structure of alaw_3 is

	component alaw_nl_l
		port(
			data			:in			std_logic;						--pcm signal a
			clock			:in			std_logic;						--clock signal
			framea		:in			std_logic;						--serial convert to paralell's frame synchronous signal
			frameb		:in			std_logic;						--inversion and 8->12's frame synchronous signal
			ebi			:in			std_logic;						--enable even bit(a-law) inversion.1:inverted;0:not inverted
			dataq			:out			std_logic_vector(12 downto 0));	--output overlap signal
	end component;

	component alaw_overlap
		port(
			dataa			:in			std_logic_vector(12 downto 0);	--pcm signal a
			datab			:in			std_logic_vector(12 downto 0);	--pcm signal b	
			frame			:in			std_logic;
			dataq			:out			std_logic_vector(12 downto 0));	--output overlap signal
	end component;

	component alaw_l_nl
		port(
			data			:in			std_logic_vector(12 downto 0);	--pcm signal a
			clock			:in			std_logic;							--clock signal
			frame			:in			std_logic;							--frame synchronous signal
			ebi			:in			std_logic;						--even bit inversion control
			dataq			:out			std_logic);						--output overlap signal
	end component;

--   signal data_l_in2						:std_logic_vector(12 downto 0);
   signal data_l_in1						:std_logic_vector(12 downto 0);
   signal data_l_in0						:std_logic_vector(12 downto 0);
   signal data_l_in_loc				 	:std_logic_vector(12 downto 0);

--	signal data_l_o_in2				 	:std_logic_vector(12 downto 0);
   signal data_l_o_in1				 	:std_logic_vector(12 downto 0);
   signal data_l_o_in0				 	:std_logic_vector(12 downto 0);
   signal data_l_o_in_loc			 	:std_logic_vector(12 downto 0);

--	signal data_l_s2						:std_logic_vector(12 downto 0);
--   signal data_l_s1						:std_logic_vector(12 downto 0);
--   signal data_l_s0						:std_logic_vector(12 downto 0);
--   signal data_l_s_loc					:std_logic_vector(12 downto 0);	

--   signal data2							:std_logic_vector(12 downto 0);
--	signal data1							:std_logic_vector(12 downto 0);
--   signal data0							:std_logic_vector(12 downto 0);	
signal tmpframe : std_logic;


begin
--	tmpframe<=not tframe(1);	 --v3.11
				tmpframe<= tframe(0); --v3.10
	
	u_alaw_nl_l_0:alaw_nl_l
		port map(
				data 		=> rdata(0),
				clock		=> rclock(0),
				framea	=> rframe(0),
				frameb	=> rframe(0),
				ebi		=>	ebi,
				dataq 	=> data_l_in0);
					
	u_alaw_nl_l_1:alaw_nl_l
		port map(
				data 		=> rdata(1),
				clock		=> rclock(1),
				framea	=> rframe(1),
				frameb	=> rframe(1),
				ebi		=>	ebi,
				dataq 	=> data_l_in1);
				
	u_alaw_nl_l_loc:alaw_nl_l
		port map(
				data 		=> tdata_loc,
				clock		=> clock_loc,
				framea	=> frame_loc,
				frameb	=> frame_loc,
				ebi		=>	ebi,
				dataq 	=> data_l_in_loc);

   u_alaw_overlap_0:alaw_overlap
	   port map(
				dataa 	=>	data_l_in_loc,
				datab 	=>	data_l_in1,
				frame 	=> tframe(0),
         	dataq 	=> data_l_o_in0);

   u_alaw_overlap_1:alaw_overlap
	   port map(
				dataa 	=>	data_l_in0,
				datab 	=>	data_l_in_loc,
				frame 	=>	tmpframe,
         	dataq 	=> data_l_o_in1);

    u_alaw_overlap_3_loc:alaw_overlap
	   port map(
				dataa 	=>	data_l_in0,
				datab 	=>	data_l_in1,
				frame 	=> frame_loc,
        		dataq 	=> data_l_o_in_loc);

	u_alaw_l_nl_0:alaw_l_nl
		port map(
				data		=> data_l_o_in0,
				clock		=> tclock(0),
				frame		=> tframe(0),
				ebi		=>	ebi,
				dataq		=> tdata(0));

	u_alaw_l_nl_1:alaw_l_nl
		port map(
				data		=> data_l_o_in1,
				clock		=> tclock(1),
				frame		=> tframe(1),
				ebi		=>	ebi,
				dataq		=> tdata(1));

	u_alaw_l_nl_loc:alaw_l_nl
		port map(
				data		=> data_l_o_in_loc,
				clock		=> clock_loc,
				frame		=> frame_loc,
				ebi		=>	ebi,
				dataq		=> rdata_loc);
end structure;