p_s.vhd

使用VHDL实现通信脉冲编码调制（PCM）中的a律转换

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity p_s is
		PORT(
			data			:in			std_logic_vector(7 downto 0);	--8bit parallel signal
			clock			:in			std_logic;						--clock signal	
			frame			:in			std_logic;
			dataq			:out		std_logic);						--output serial signal
end p_s;

architecture rtl of p_s is	
	signal	data_pre		:std_logic_vector(7 downto 0);
	signal 	counter			:std_logic_vector(2 downto 0);--integer range 7 downto 0 ;
begin
	process(clock,frame)
	begin
		if frame = '1' then
			counter <= "000";
		elsif clock'event and clock = '1' then
			counter <= counter + '1';
		end if;
	end process;

	process(frame)
	begin
		if frame'event and frame = '1' then
			data_pre <= data;
		end if;
	end process;

	with counter select
		dataq <= data_pre(7)	when "000",
				 data_pre(6)	when "001",
				 data_pre(5)	when "010",
				 data_pre(4)	when "011",
				 data_pre(3)	when "100",
				 data_pre(2)	when "101",
				 data_pre(1)	when "110",
				 data_pre(0)	when others;

end rtl;