alaw_13_8.vhd

使用VHDL实现通信脉冲编码调制（PCM）中的a律转换

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;

entity alaw_13_8 is
		PORT(
			data			:in			std_logic_vector(12 downto 0);	--pcm linear signal
			frame			:in			std_logic;						--frame synchronous signal
			dataq			:out		std_logic_vector(7 downto 0));	--output noliear signal
end alaw_13_8;

architecture rtl of alaw_13_8 is
	signal	data_in			:std_logic_vector(6 downto 0);
begin
	process(data)
	begin
		if data(11) = '1' then
			data_in <= "111" & data(10 downto 7);
		elsif data(10) = '1' then
			data_in <= "110" & data(9 downto 6);
		elsif data(9) = '1' then
			data_in <= "101" & data(8 downto 5);
		elsif data(8) = '1' then
			data_in <= "100" & data(7 downto 4);
		elsif data(7) = '1' then
			data_in <= "011" & data(6 downto 3);
		elsif data(6) = '1' then
			data_in <= "010" & data(5 downto 2);
		elsif data(5) = '1' then
			data_in <= "001" & data(4 downto 1);
		else
			data_in <= "000" & data(4 downto 1);
		end if;	
	end process;
				
	process(frame)
	begin
		if frame'event and frame = '1' then
			dataq <= data(12) & data_in;
		end if;
	end process;
end rtl;