alaw_overlap.vhd

使用VHDL实现通信脉冲编码调制（PCM）中的a律转换

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity alaw_overlap is
	port(
		dataa			:in			std_logic_vector(12 downto 0);		--pcm signal a
		datab			:in			std_logic_vector(12 downto 0);		--pcm signal b
		frame			:in			std_logic;
		dataq			:out		std_logic_vector(12 downto 0));		--output overlap signal
end alaw_overlap;

architecture rtl of alaw_overlap is
	signal		sign		:std_logic;									--sign bit
	signal		xor_sign	:std_logic;									--xor sign bit
	signal		sel_sign	:std_logic;									--compare a and b
	signal		sel_code_a	:std_logic;									--select a or un_a
	signal		sel_code_b	:std_logic;									--select b or un_b
	signal		un_a		:std_logic_vector(11 downto 0);				--not a[n-2..0]
	signal		un_b		:std_logic_vector(11 downto 0);				--not b[n-2..0]
	signal		code_a		:std_logic_vector(11 downto 0);				--code_a[n-2..0]
	signal		code_b		:std_logic_vector(11 downto 0);				--code_b[n-2..0]
	signal		code		:std_logic_vector(11 downto 0);				--code[n-2..0]
	signal		integer_a	:integer	range 4095 downto 0;
	signal		integer_b	:integer	range 4095 downto 0;
	signal		code_tmp	:std_logic_vector(12 downto 0);				--code_a[n-2..0]
	signal		dataq_in	:std_logic_vector(12 downto 0);
begin
	integer_a <= conv_integer(dataa(11 downto 0));		--convert dataa to integer type;
	integer_b <= conv_integer(datab(11 downto 0));		--convert datab to integer type;

	un_a <= not dataa(11 downto 0) + '1';		
	un_b <= not datab(11 downto 0) + '1';

	sel_sign <= '1' when integer_a > integer_b else
 				'0';

	sign <= dataa(12) when sel_sign = '1' else
			datab(12);

	xor_sign <= dataa(12) xor datab(12);

	sel_code_a <= xor_sign and (not sel_sign);
	sel_code_b <= xor_sign and sel_sign;

	code_a <= dataa(11 downto 0) when sel_code_a = '0' else	un_a;
	code_b <= datab(11 downto 0) when sel_code_b = '0' else un_b;
	
	code_tmp <= ('0' & code_a) + ('0' & code_b) ;

	code <= code_tmp(11 downto 0)		when	code_tmp(12) = '0' or xor_sign = '1' else
			"111111111111";	 
	
	dataq_in <=	dataa			when	datab = "0000000000000" else
--	dataq <=	datab			when	dataa = "0000000000000" else
			 		sign & code;
	
	process(frame)
	begin
		if rising_edge(frame) then
			dataq <= dataq_in;
		end if;
	end process;

end rtl;