alaw_8_13.vhd

使用VHDL实现通信脉冲编码调制（PCM）中的a律转换

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;

entity alaw_8_13 is
		PORT(
			data			:in			std_logic_vector(7 downto 0);	--pcm signal a
			frame			:in			std_logic;						--frame synchronous signal
			dataq			:out		std_logic_vector(12 downto 0));	--output overlap signal
end alaw_8_13;

architecture rtl of alaw_8_13 is
begin
	process(frame)
	begin
		if frame'event and frame = '1' then
			if data(6 downto 0) = "0000000" then 
				dataq(11 downto 0) <= "0000000" & data(3 downto 0) & '0';				
			else CASE data(6 downto 4) IS
					WHEN "000" =>
						dataq(11 downto 0) <= "0000000" & data(3 downto 0) & '1';	
					WHEN "001" =>
						dataq(11 downto 0) <= "0000001" & data(3 downto 0) & '1';
					WHEN "010" =>
						dataq(11 downto 0) <= "000001" & data(3 downto 0) & "10";
					WHEN "011" =>
						dataq(11 downto 0) <= "00001" & data(3 downto 0) & "100";
					WHEN "100" =>
						dataq(11 downto 0) <= "0001" & data(3 downto 0) & "1000";
					WHEN "101" =>
						dataq(11 downto 0) <= "001" & data(3 downto 0) & "10000";
					WHEN "110" =>
						dataq(11 downto 0) <= "01" & data(3 downto 0) & "100000";
					WHEN others =>
						dataq(11 downto 0) <= '1' & data(3 downto 0) & "1000000";
				END CASE;
			end if;
			
			dataq(12) <= data(7);
		end if;
	end process;
end rtl;