struct.bd

Modelsim FLI接口设计实例

r 10
tg (CPTG
uid 133,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 134,0
va (VaSet
)
xt "33000,21500,34300,22500"
st "tdre"
blo "33000,22300"
)
)
)
*36 (CptPort
uid 135,0
ps "OnEdgeStrategy"
shape (Triangle
uid 136,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "50000,22625,50750,23375"
)
n "tx"
t "std_logic"
m 1
o 7
r 11
tg (CPTG
uid 137,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 138,0
va (VaSet
)
xt "48500,22500,49000,23500"
st "tx"
ju 2
blo "49000,23300"
)
)
)
*37 (CptPort
uid 139,0
ps "OnEdgeStrategy"
shape (Triangle
uid 140,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "50000,32625,50750,33375"
)
n "txclk"
t "std_logic"
o 7
r 12
tg (CPTG
uid 141,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 142,0
va (VaSet
)
xt "47600,32500,49000,33500"
st "txclk"
ju 2
blo "49000,33300"
)
)
)
*38 (CptPort
uid 143,0
ps "OnEdgeStrategy"
shape (Triangle
uid 144,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "31250,23625,32000,24375"
)
n "wr"
t "std_logic"
o 7
r 13
tg (CPTG
uid 145,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 146,0
va (VaSet
)
xt "33000,23500,33800,24500"
st "wr"
blo "33000,24300"
)
)
)
]
shape (Rectangle
uid 149,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "32000,20000,50000,35000"
)
ttg (MlTextGroup
uid 150,0
optionalChildren [
*39 (Text
uid 147,0
va (VaSet
font "Arial,8,1"
)
xt "41400,29000,43600,30000"
st "struct"
blo "41400,29800"
tm "SaCptArchNameMgr"
)
]
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*40 (Text
uid 151,0
va (VaSet
font "Arial,8,1"
)
xt "41400,26000,45200,27000"
st "UART_FLI"
blo "41400,26800"
)
*41 (Text
uid 152,0
va (VaSet
font "Arial,8,1"
)
xt "41400,27000,42900,28000"
st "uart"
blo "41400,27800"
)
*42 (Text
uid 153,0
va (VaSet
font "Arial,8,1"
)
xt "41400,28000,42000,29000"
st "I1"
blo "41400,28800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 154,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 155,0
text (MLText
uid 156,0
va (VaSet
font "Courier New,8,0"
)
xt "17000,15000,17000,15000"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
sIVOD 1
)
archName "struct"
archType 2
archFileType "BLOCK_DIAGRAM"
)
*43 (Net
uid 157,0
name "tdre"
type "std_logic"
orderNo 1
declText (MLText
uid 158,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,11800,36500,12600"
st "SIGNAL tdre    : std_logic"
)
)
*44 (Net
uid 163,0
name "wr"
type "std_logic"
orderNo 2
declText (MLText
uid 164,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,12600,36500,13400"
st "SIGNAL wr      : std_logic"
)
)
*45 (Net
uid 169,0
name "rdrf"
type "std_logic"
orderNo 3
declText (MLText
uid 170,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,11000,36500,11800"
st "SIGNAL rdrf    : std_logic"
)
)
*46 (Net
uid 175,0
name "rd"
type "std_logic"
orderNo 4
declText (MLText
uid 176,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,10200,36500,11000"
st "SIGNAL rd      : std_logic"
)
)
*47 (Net
uid 181,0
name "clk"
type "std_logic"
orderNo 5
declText (MLText
uid 182,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,2000,32500,2800"
st "clk     : std_logic"
)
)
*48 (Net
uid 189,0
name "resetn"
type "std_logic"
orderNo 6
declText (MLText
uid 190,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,2800,32500,3600"
st "resetn  : std_logic"
)
)
*49 (Net
uid 197,0
name "dbusin"
type "std_logic_vector"
bounds "(7 DOWNTO 0)"
orderNo 7
declText (MLText
uid 198,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,8600,46500,9400"
st "SIGNAL dbusin  : std_logic_vector(7 DOWNTO 0)"
)
)
*50 (Net
uid 203,0
name "dbusout"
type "std_logic_vector"
bounds "(7 DOWNTO 0)"
orderNo 8
declText (MLText
uid 204,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,9400,46500,10200"
st "SIGNAL dbusout : std_logic_vector(7 DOWNTO 0)"
)
)
*51 (Net
uid 209,0
name "ferror"
type "std_logic"
orderNo 9
declText (MLText
uid 210,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,6000,32500,6800"
st "ferror  : std_logic"
)
)
*52 (PortIoOut
uid 215,0
shape (CompositeShape
uid 216,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 217,0
sl 0
ro 270
xt "60500,20625,62000,21375"
)
(Line
uid 218,0
sl 0
ro 270
xt "60000,21000,60500,21000"
pts [
"60000,21000"
"60500,21000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 219,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 220,0
va (VaSet
)
xt "63000,20500,64900,21500"
st "ferror"
blo "63000,21300"
tm "WireNameMgr"
)
)
)
*53 (Net
uid 221,0
name "tx"
type "std_logic"
orderNo 10
declText (MLText
uid 222,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,6800,32500,7600"
st "tx      : std_logic"
)
)
*54 (PortIoOut
uid 227,0
shape (CompositeShape
uid 228,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 229,0
sl 0
ro 270
xt "60500,22625,62000,23375"
)
(Line
uid 230,0
sl 0
ro 270
xt "60000,23000,60500,23000"
pts [
"60000,23000"
"60500,23000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 231,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 232,0
va (VaSet
)
xt "63000,22500,63500,23500"
st "tx"
blo "63000,23300"
tm "WireNameMgr"
)
)
)
*55 (Net
uid 233,0
name "rx"
type "std_logic"
orderNo 11
declText (MLText
uid 234,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,3600,32500,4400"
st "rx      : std_logic"
)
)
*56 (PortIoIn
uid 239,0
shape (CompositeShape
uid 240,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 241,0
sl 0
ro 90
xt "60500,24625,62000,25375"
)
(Line
uid 242,0
sl 0
ro 90
xt "60000,25000,60500,25000"
pts [
"60500,25000"
"60000,25000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 243,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 244,0
va (VaSet
)
xt "63000,24500,63600,25500"
st "rx"
blo "63000,25300"
tm "WireNameMgr"
)
)
)
*57 (PortIoIn
uid 251,0
shape (CompositeShape
uid 252,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 253,0
sl 0
ro 90
xt "60500,26625,62000,27375"
)
(Line
uid 254,0
sl 0
ro 90
xt "60000,27000,60500,27000"
pts [
"60500,27000"
"60000,27000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 255,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 256,0
va (VaSet
)
xt "63000,26500,65100,27500"
st "resetn"
blo "63000,27300"
tm "WireNameMgr"
)
)
)
*58 (PortIoIn
uid 263,0
shape (CompositeShape
uid 264,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 265,0
sl 0
ro 90
xt "60500,28625,62000,29375"
)
(Line
uid 266,0
sl 0
ro 90
xt "60000,29000,60500,29000"
pts [
"60500,29000"
"60000,29000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 267,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 268,0
va (VaSet
)
xt "63000,28500,63900,29500"
st "clk"
blo "63000,29300"
tm "WireNameMgr"
)
)
)
*59 (Net
uid 269,0
name "rxclk16"
type "std_logic"
orderNo 14
declText (MLText
uid 270,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,4400,32500,5200"
st "rxclk16 : std_logic"
)
)
*60 (PortIoIn
uid 275,0
shape (CompositeShape
uid 276,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 277,0
sl 0
ro 90
xt "60500,30625,62000,31375"
)
(Line
uid 278,0
sl 0
ro 90
xt "60000,31000,60500,31000"
pts [
"60500,31000"
"60000,31000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 279,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 280,0
va (VaSet
)
xt "63000,30500,65300,31500"
st "rxclk16"
blo "63000,31300"
tm "WireNameMgr"
)
)
)
*61 (Net
uid 281,0
name "txclk"
type "std_logic"
orderNo 15
declText (MLText
uid 282,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,5200,32500,6000"
st "txclk   : std_logic"
)
)
*62 (PortIoIn
uid 287,0
shape (CompositeShape
uid 288,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 289,0
sl 0
ro 90
xt "60500,32625,62000,33375"
)
(Line
uid 290,0
sl 0
ro 90
xt "60000,33000,60500,33000"
pts [
"60500,33000"
"60000,33000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 291,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 292,0
va (VaSet
)
xt "63000,32500,64400,33500"
st "txclk"
blo "63000,33300"
tm "WireNameMgr"
)
)
)
*63 (Wire
uid 159,0
shape (OrthoPolyLine
uid 160,0
va (VaSet
vasetType 3
)
xt "24750,22000,31250,22000"
pts [
"31250,22000"
"24750,22000"
]
)
start &35
end &18
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 161,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 162,0
va (VaSet
)
xt "27000,21000,28300,22000"
st "tdre"
blo "27000,21800"
tm "WireNameMgr"
)
)
on &43
)
*64 (Wire
uid 165,0
shape (OrthoPolyLine
uid 166,0
va (VaSet
vasetType 3
)
xt "24750,24000,31250,24000"
pts [
"24750,24000"
"31250,24000"
]
)
start &19
end &38
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 167,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 168,0
va (VaSet
)
xt "26750,23000,27550,24000"
st "wr"
blo "26750,23800"
tm "WireNameMgr"
)
)
on &44
)
*65 (Wire
uid 171,0
shape (OrthoPolyLine
uid 172,0
va (VaSet
vasetType 3
)
xt "24750,29000,31250,29000"
pts [
"31250,29000"
"24750,29000"
]
)
start &31
end &16
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 173,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 174,0
va (VaSet
)
xt "27000,28000,28200,29000"
st "rdrf"
blo "27000,28800"
tm "WireNameMgr"
)
)
on &45
)
*66 (Wire
uid 177,0
shape (OrthoPolyLine
uid 178,0
va (VaSet
vasetType 3
)
xt "24750,31000,31250,31000"
pts [
"24750,31000"
"31250,31000"
]
)
start &15
end &28
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 179,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 180,0
va (VaSet
)
xt "26750,30000,27450,31000"
st "rd"
blo "26750,30800"
tm "WireNameMgr"
)
)
on &46
)
*67 (Wire
uid 183,0
shape (OrthoPolyLine
uid 184,0
va (VaSet
vasetType 3
)
xt "10000,22000,13250,22000"
pts [
"10000,22000"
"13250,22000"
]
)
end &20
sat 16
eat 32
st 0
si 0
tg (WTG
uid 187,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 188,0
va (VaSet
)
xt "11000,21000,11900,22000"
st "clk"
blo "11000,21800"
tm "WireNameMgr"
)
)
on &47
)
*68 (Wire
uid 191,0
shape (OrthoPolyLine
uid 192,0
va (VaSet
vasetType 3
)
xt "10000,24000,13250,24000"
pts [
"10000,24000"
"13250,24000"
]
)
end &17
sat 16
eat 32
st 0
si 0
tg (WTG
uid 195,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 196,0
va (VaSet
)
xt "11000,23000,13100,24000"
st "resetn"
blo "11000,23800"
tm "WireNameMgr"
)
)
on &48
)
*69 (Wire
uid 199,0
shape (OrthoPolyLine
uid 200,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "24750,26000,31250,26000"
pts [
"24750,26000"
"31250,26000"
]
)
start &13
end &32
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 201,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 202,0
va (VaSet
)
xt "26750,25000,28950,26000"
st "dbusin"
blo "26750,25800"
tm "WireNameMgr"
)
)
on &49
)
*70 (Wire
uid 205,0
shape (OrthoPolyLine
uid 206,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "24750,33000,31250,33000"
pts [
"24750,33000"
"31250,33000"
]
)
start &14
end &27
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 207,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 208,0
va (VaSet
)
xt "26750,32000,29350,33000"
st "dbusout"
blo "26750,32800"
tm "WireNameMgr"
)
)
on &50
)
*71 (Wire
uid 211,0
shape (OrthoPolyLine
uid 212,0
va (VaSet
vasetType 3
)
xt "50750,21000,60000,21000"
pts [
"50750,21000"
"60000,21000"
]
)
start &30
end &52
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 213,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 214,0
va (VaSet
isHidden 1
)
xt "52750,20000,54650,21000"
st "ferror"
blo "52750,20800"
tm "WireNameMgr"
)
)
on &51
)
*72 (Wire
uid 223,0
shape (OrthoPolyLine
uid 224,0
va (VaSet
vasetType 3
)
xt "50750,23000,60000,23000"
pts [
"50750,23000"
"60000,23000"
]
)
start &36
end &54
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 225,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 226,0
va (VaSet
isHidden 1
)
xt "52750,22000,53250,23000"
st "tx"
blo "52750,22800"
tm "WireNameMgr"
)
)
on &53
)
*73 (Wire
uid 235,0
shape (OrthoPolyLine
uid 236,0
va (VaSet
vasetType 3
)
xt "50750,25000,60000,25000"
pts [
"60000,25000"
"50750,25000"
]
)
start &56
end &33
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 237,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 238,0
va (VaSet
isHidden 1
)
xt "58000,24000,58600,25000"
st "rx"
blo "58000,24800"
tm "WireNameMgr"
)
)
on &55
)
*74 (Wire
uid 247,0
shape (OrthoPolyLine
uid 248,0
va (VaSet
vasetType 3
)
xt "50750,27000,60000,27000"
pts [
"50750,27000"
"60000,27000"
]
)
start &29
end &57
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 249,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 250,0
va (VaSet
isHidden 1
)
xt "52750,26000,54850,27000"
st "resetn"
blo "52750,26800"
tm "WireNameMgr"
)
)
on &48
)
*75 (Wire
uid 259,0
shape (OrthoPolyLine
uid 260,0
va (VaSet
vasetType 3
)
xt "50750,29000,60000,29000"
pts [
"50750,29000"
"60000,29000"
]
)
start &26
end &58
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 261,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 262,0
va (VaSet
isHidden 1
)
xt "52750,28000,53650,29000"
st "clk"
blo "52750,28800"
tm "WireNameMgr"
)
)
on &47
)
*76 (Wire
uid 271,0
shape (OrthoPolyLine
uid 272,0
va (VaSet
vasetType 3
)
xt "50750,31000,60000,31000"
pts [
"50750,31000"
"60000,31000"
]