struct.bd

Modelsim FLI接口设计实例

DocumentHdrVersion "1.1"
Header (DocumentHdr
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
]
instances [
(Instance
name "I0"
duLibraryName "UART_FLI"
duName "fli_socket"
archName "behaviour"
archFileType 9
elements [
]
mwi 0
uid 86,0
)
(Instance
name "I1"
duLibraryName "UART_FLI"
duName "uart"
archName "struct"
archFileType 1
elements [
]
mwi 0
uid 148,0
)
]
)
version "21.1"
appVersion "2003.2 (Build 28)"
noEmbeddedEditors 1
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(vvPair
variable "HDLDir"
value "D:\\HT86\\UART_FLI\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\HT86\\UART_FLI\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "D:\\HT86\\UART_FLI\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "config"
value "%(unit)_config"
)
(vvPair
variable "d"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top"
)
(vvPair
variable "d_logical"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top"
)
(vvPair
variable "date"
value "13/09/2003"
)
(vvPair
variable "day"
value "Sat"
)
(vvPair
variable "day_long"
value "Saturday"
)
(vvPair
variable "dd"
value "13"
)
(vvPair
variable "entity_name"
value "uart_fli_top"
)
(vvPair
variable "ext"
value "bd"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "ACHILLES"
)
(vvPair
variable "library"
value "UART_FLI"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "D:/HT86/UART_FLI/work/"
)
(vvPair
variable "mm"
value "09"
)
(vvPair
variable "module_name"
value "uart_fli_top"
)
(vvPair
variable "month"
value "Sep"
)
(vvPair
variable "month_long"
value "September"
)
(vvPair
variable "p"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top\\struct.bd"
)
(vvPair
variable "p_logical"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top\\struct.bd"
)
(vvPair
variable "project_name"
value "HT86"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "<TBD>"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "D:/PRODUCTS/PRECISIONSYNTHESIS2003/MGC_HOME/BIN"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "time"
value "10:12:29"
)
(vvPair
variable "unit"
value "uart_fli_top"
)
(vvPair
variable "user"
value "Hans"
)
(vvPair
variable "version"
value "2003.2 (Build 28)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2003"
)
(vvPair
variable "yy"
value "03"
)
]
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shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "24000,25625,24750,26375"
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n "dbusin"
t "std_logic_vector"
b "(7 DOWNTO 0)"
m 1
o 9
r 6
tg (CPTG
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f (Text
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r 3
tg (CPTG
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t "std_logic"
o 11
r 4
tg (CPTG
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stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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t "std_logic"
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r 5
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r 8
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shape (Triangle
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va (VaSet
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fg "0,65535,0"
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xt "13250,21625,14000,22375"
)
n "clk"
t "std_logic"
o 14
r 1
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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ttg (MlTextGroup
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tm "SaCptArchNameMgr"
)
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textVec [
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header ""
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elements [
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portVis (PortSigDisplay
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archName "behaviour"
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r 1
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m 1
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r 5
tg (CPTG
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o 6
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o 7
r 7
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o 7
r 8
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)
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ro 270
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)
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)
n "rxclk16"
t "std_logic"
o 7
r 9
tg (CPTG
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f (Text
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va (VaSet
)
xt "46700,30500,49000,31500"
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ju 2
blo "49000,31300"
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)
)
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
vasetType 1
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xt "31250,21625,32000,22375"
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n "tdre"
t "std_logic"
m 1
o 7