struct.bd

Modelsim FLI接口设计实例

shape (Triangle
uid 100,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,32625,40750,33375"
)
n "txclk"
t "std_logic"
o 2
r 0
tg (CPTG
uid 101,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 102,0
va (VaSet
)
xt "37600,32500,39000,33500"
st "txclk"
ju 2
blo "39000,33300"
)
)
)
*28 (CptPort
uid 107,0
ps "OnEdgeStrategy"
shape (Triangle
uid 108,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28250,29625,29000,30375"
)
n "dbus"
t "std_logic_vector"
b "(7 downto 0)"
o 4
r 0
tg (CPTG
uid 109,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 110,0
va (VaSet
)
xt "30000,29500,34600,30500"
st "dbus : (7:0)"
blo "30000,30300"
)
)
)
*29 (CptPort
uid 111,0
ps "OnEdgeStrategy"
shape (Triangle
uid 112,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28250,33625,29000,34375"
)
n "tdre"
t "std_logic"
m 1
o 5
r 0
tg (CPTG
uid 113,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 114,0
va (VaSet
)
xt "30000,33500,31300,34500"
st "tdre"
blo "30000,34300"
)
)
)
*30 (CptPort
uid 115,0
ps "OnEdgeStrategy"
shape (Triangle
uid 116,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28250,31625,29000,32375"
)
n "wr"
t "std_logic"
o 6
r 0
tg (CPTG
uid 117,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 118,0
va (VaSet
)
xt "30000,31500,30800,32500"
st "wr"
blo "30000,32300"
)
)
)
*31 (CptPort
uid 119,0
ps "OnEdgeStrategy"
shape (Triangle
uid 120,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,29625,40750,30375"
)
n "tx"
t "std_logic"
m 1
o 7
r 0
tg (CPTG
uid 121,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 122,0
va (VaSet
)
xt "38500,29500,39000,30500"
st "tx"
ju 2
blo "39000,30300"
)
)
)
*32 (CptPort
uid 603,0
ps "OnEdgeStrategy"
shape (Triangle
uid 604,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28250,35625,29000,36375"
)
n "resetn"
t "std_logic"
o 3
r 0
tg (CPTG
uid 605,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 606,0
va (VaSet
)
xt "30000,35500,32100,36500"
st "resetn"
blo "30000,36300"
)
)
)
]
shape (Rectangle
uid 125,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "29000,27000,40000,37000"
)
oxt "28000,30000,38000,36000"
ttg (MlTextGroup
uid 126,0
optionalChildren [
*33 (Text
uid 123,0
va (VaSet
font "Arial,8,1"
)
xt "33100,34000,36500,35000"
st "synthesis"
blo "33100,34800"
tm "SaCptArchNameMgr"
)
]
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*34 (Text
uid 127,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "33100,31000,36900,32000"
st "UART_FLI"
blo "33100,31800"
)
*35 (Text
uid 128,0
va (VaSet
font "Arial,8,1"
)
xt "33100,32000,35300,33000"
st "uarttx"
blo "33100,32800"
)
*36 (Text
uid 129,0
va (VaSet
font "Arial,8,1"
)
xt "33100,33000,33700,34000"
st "I1"
blo "33100,33800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 130,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 131,0
text (MLText
uid 132,0
va (VaSet
font "Courier New,8,0"
)
xt "34500,25000,34500,25000"
)
header ""
)
elements [
]
)
ordering 1
connectByName 1
portVis (PortSigDisplay
)
archName "synthesis"
archType 2
archFileType "VHDL_TEXT"
)
*37 (Net
uid 133,0
name "clk"
type "std_logic"
orderNo 1
declText (MLText
uid 134,0
va (VaSet
font "Courier New,8,0"
)
xt "15000,2400,25500,3200"
st "clk     : std_logic"
)
)
*38 (PortIoIn
uid 139,0
shape (CompositeShape
uid 140,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 141,0
sl 0
ro 270
xt "12000,16625,13500,17375"
)
(Line
uid 142,0
sl 0
ro 270
xt "13500,17000,14000,17000"
pts [
"13500,17000"
"14000,17000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 143,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 144,0
va (VaSet
)
xt "10100,16500,11000,17500"
st "clk"
ju 2
blo "11000,17300"
tm "WireNameMgr"
)
)
)
*39 (Net
uid 157,0
name "resetn"
type "std_logic"
orderNo 3
declText (MLText
uid 158,0
va (VaSet
font "Courier New,8,0"
)
xt "15000,4800,25500,5600"
st "resetn  : std_logic"
)
)
*40 (PortIoIn
uid 163,0
shape (CompositeShape
uid 164,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 165,0
sl 0
ro 270
xt "12000,20625,13500,21375"
)
(Line
uid 166,0
sl 0
ro 270
xt "13500,21000,14000,21000"
pts [
"13500,21000"
"14000,21000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 167,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 168,0
va (VaSet
)
xt "8900,20500,11000,21500"
st "resetn"
ju 2
blo "11000,21300"
tm "WireNameMgr"
)
)
)
*41 (Net
uid 169,0
name "rd"
type "std_logic"
orderNo 4
declText (MLText
uid 170,0
va (VaSet
font "Courier New,8,0"
)
xt "15000,4000,25500,4800"
st "rd      : std_logic"
)
)
*42 (PortIoIn
uid 175,0
shape (CompositeShape
uid 176,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 177,0
sl 0
ro 270
xt "12000,22625,13500,23375"
)
(Line
uid 178,0
sl 0
ro 270
xt "13500,23000,14000,23000"
pts [
"13500,23000"
"14000,23000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 179,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 180,0
va (VaSet
)
xt "10300,22500,11000,23500"
st "rd"
ju 2
blo "11000,23300"
tm "WireNameMgr"
)
)
)
*43 (PortIoOut
uid 217,0
shape (CompositeShape
uid 218,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 219,0
sl 0
ro 270
xt "53500,16625,55000,17375"
)
(Line
uid 220,0
sl 0
ro 270
xt "53000,17000,53500,17000"
pts [
"53000,17000"
"53500,17000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 221,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 222,0
va (VaSet
)
xt "56000,16500,58600,17500"
st "dbusout"
blo "56000,17300"
tm "WireNameMgr"
)
)
)
*44 (Net
uid 237,0
name "dbusout"
type "std_logic_vector"
bounds "(7 DOWNTO 0)"
orderNo 6
declText (MLText
uid 238,0
va (VaSet
font "Courier New,8,0"
)
xt "15000,8800,35500,9600"
st "dbusout : std_logic_vector(7 DOWNTO 0)"
)
)
*45 (Net
uid 287,0
name "ferror"
type "std_logic"
orderNo 11
declText (MLText
uid 288,0
va (VaSet
font "Courier New,8,0"
)
xt "15000,9600,25500,10400"
st "ferror  : std_logic"
)
)
*46 (PortIoOut
uid 293,0
shape (CompositeShape
uid 294,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 295,0
sl 0
ro 270
xt "53500,20625,55000,21375"
)
(Line
uid 296,0
sl 0
ro 270
xt "53000,21000,53500,21000"
pts [
"53000,21000"
"53500,21000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 297,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 298,0
va (VaSet
)
xt "56000,20500,57900,21500"
st "ferror"
blo "56000,21300"
tm "WireNameMgr"
)
)
)
*47 (Net
uid 299,0
name "rdrf"
type "std_logic"
orderNo 12
declText (MLText
uid 300,0
va (VaSet
font "Courier New,8,0"
)
xt "15000,10400,25500,11200"
st "rdrf    : std_logic"
)
)
*48 (PortIoOut
uid 305,0
shape (CompositeShape
uid 306,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 307,0
sl 0
ro 270
xt "53500,18625,55000,19375"
)
(Line
uid 308,0
sl 0
ro 270
xt "53000,19000,53500,19000"
pts [
"53000,19000"
"53500,19000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 309,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 310,0
va (VaSet
)
xt "56000,18500,57200,19500"
st "rdrf"
blo "56000,19300"
tm "WireNameMgr"
)
)
)
*49 (Net
uid 499,0
name "rx"
type "std_logic"
orderNo 9
declText (MLText
uid 500,0
va (VaSet
font "Courier New,8,0"
)
xt "15000,5600,25500,6400"
st "rx      : std_logic"
)
)
*50 (PortIoIn
uid 505,0
shape (CompositeShape
uid 506,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 507,0
sl 0
ro 90
xt "53500,22625,55000,23375"
)
(Line
uid 508,0
sl 0
ro 90
xt "53000,23000,53500,23000"
pts [
"53500,23000"
"53000,23000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 509,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 510,0
va (VaSet
)
xt "56000,22500,56600,23500"
st "rx"
blo "56000,23300"
tm "WireNameMgr"
)
)
)
*51 (Net
uid 511,0
name "tx"
type "std_logic"
orderNo 10
declText (MLText
uid 512,0
va (VaSet
font "Courier New,8,0"
)
xt "15000,12000,25500,12800"
st "tx      : std_logic"
)
)
*52 (PortIoOut
uid 517,0
shape (CompositeShape
uid 518,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 519,0
sl 0
ro 270
xt "53500,29625,55000,30375"
)
(Line
uid 520,0
sl 0
ro 270
xt "53000,30000,53500,30000"
pts [
"53000,30000"
"53500,30000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 521,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 522,0
va (VaSet
)
xt "56000,29500,56500,30500"
st "tx"
blo "56000,30300"
tm "WireNameMgr"
)
)
)
*53 (Net
uid 523,0
name "tdre"
type "std_logic"
orderNo 11
declText (MLText
uid 524,0
va (VaSet
font "Courier New,8,0"
)
xt "15000,11200,25500,12000"
st "tdre    : std_logic"
)
)
*54 (PortIoOut
uid 529,0
shape (CompositeShape
uid 530,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 531,0
sl 0
ro 90
xt "12000,33625,13500,34375"
)
(Line
uid 532,0
sl 0
ro 90
xt "13500,34000,14000,34000"
pts [
"14000,34000"
"13500,34000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 533,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 534,0
va (VaSet
)
xt "9700,33500,11000,34500"
st "tdre"
ju 2
blo "11000,34300"
tm "WireNameMgr"
)
)
)
*55 (Net
uid 535,0
name "wr"
type "std_logic"
orderNo 12
declText (MLText
uid 536,0
va (VaSet
font "Courier New,8,0"
)
xt "15000,8000,25500,8800"
st "wr      : std_logic"
)
)
*56 (PortIoIn
uid 541,0
shape (CompositeShape
uid 542,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 543,0
sl 0
ro 270
xt "12000,31625,13500,32375"
)
(Line
uid 544,0
sl 0
ro 270
xt "13500,32000,14000,32000"
pts [
"13500,32000"
"14000,32000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 545,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 546,0
va (VaSet
)
xt "10200,31500,11000,32500"
st "wr"
ju 2
blo "11000,32300"
tm "WireNameMgr"
)
)
)
*57 (PortIoIn
uid 553,0
shape (CompositeShape
uid 554,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 555,0
sl 0
ro 270
xt "12000,29625,13500,30375"
)
(Line
uid 556,0
sl 0
ro 270
xt "13500,30000,14000,30000"
pts [
"13500,30000"
"14000,30000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 557,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 558,0
va (VaSet
)
xt "8800,29500,11000,30500"
st "dbusin"
ju 2
blo "11000,30300"
tm "WireNameMgr"
)
)
)
*58 (PortIoIn
uid 577,0
shape (CompositeShape
uid 578,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 579,0
sl 0
ro 270