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📄 struct.bd

📁 Modelsim FLI接口设计实例
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DocumentHdrVersion "1.1"
Header (DocumentHdr
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "std_logic_unsigned"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
)
]
instances [
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name "I0"
duLibraryName "UART_FLI"
duName "uartrx"
archName "synthesis"
archFileType 9
elements [
]
mwi 0
uid 86,0
)
(Instance
name "I1"
duLibraryName "UART_FLI"
duName "uarttx"
archName "synthesis"
archFileType 9
elements [
]
mwi 0
uid 124,0
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]
)
version "21.1"
appVersion "2003.2 (Build 28)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "D:\\HT86\\UART_FLI\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\HT86\\UART_FLI\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\HT86\\UART_FLI\\hds\\uart\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\HT86\\UART_FLI\\hds\\uart\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "D:\\HT86\\UART_FLI\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "config"
value "%(unit)_config"
)
(vvPair
variable "d"
value "D:\\HT86\\UART_FLI\\hds\\uart"
)
(vvPair
variable "d_logical"
value "D:\\HT86\\UART_FLI\\hds\\uart"
)
(vvPair
variable "date"
value "13/09/2003"
)
(vvPair
variable "day"
value "Sat"
)
(vvPair
variable "day_long"
value "Saturday"
)
(vvPair
variable "dd"
value "13"
)
(vvPair
variable "entity_name"
value "uart"
)
(vvPair
variable "ext"
value "bd"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "ACHILLES"
)
(vvPair
variable "library"
value "UART_FLI"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "D:/HT86/UART_FLI/work/"
)
(vvPair
variable "mm"
value "09"
)
(vvPair
variable "module_name"
value "uart"
)
(vvPair
variable "month"
value "Sep"
)
(vvPair
variable "month_long"
value "September"
)
(vvPair
variable "p"
value "D:\\HT86\\UART_FLI\\hds\\uart\\struct.bd"
)
(vvPair
variable "p_logical"
value "D:\\HT86\\UART_FLI\\hds\\uart\\struct.bd"
)
(vvPair
variable "project_name"
value "HT86"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "<TBD>"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "D:/PRODUCTS/PRECISIONSYNTHESIS2003/MGC_HOME/BIN"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "time"
value "10:11:41"
)
(vvPair
variable "unit"
value "uart"
)
(vvPair
variable "user"
value "Hans"
)
(vvPair
variable "version"
value "2003.2 (Build 28)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2003"
)
(vvPair
variable "yy"
value "03"
)
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r 0
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m 1
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r 0
tg (CPTG
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t "std_logic"
o 8
r 0
tg (CPTG
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stg "RightVerticalLayoutStrategy"
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xt "38400,22500,39000,23500"
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ttg (MlTextGroup
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optionalChildren [
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tm "SaCptArchNameMgr"
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header ""
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elements [
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ordering 1
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