symbol.sb

Modelsim FLI接口设计实例

DocumentHdrVersion "1.1"
Header (DocumentHdr
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
]
)
version "16.1"
appVersion "2003.1 (Build 399)"
model (Symbol
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "D:\\hdl_designs\\uart\\uart_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\hdl_designs\\uart\\uart_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\hdl_designs\\uart\\uart_lib\\hds\\uarttop\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\hdl_designs\\uart\\uart_lib\\hds\\uarttop\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "D:\\hdl_designs\\uart\\uart_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "config"
value "%(unit)_config"
)
(vvPair
variable "d"
value "D:\\hdl_designs\\uart\\uart_lib\\hds\\uarttop"
)
(vvPair
variable "d_logical"
value "D:\\hdl_designs\\uart\\uart_lib\\hds\\uarttop"
)
(vvPair
variable "date"
value "05/08/2003"
)
(vvPair
variable "day"
value "Tue"
)
(vvPair
variable "day_long"
value "Tuesday"
)
(vvPair
variable "dd"
value "05"
)
(vvPair
variable "entity_name"
value "uarttop"
)
(vvPair
variable "ext"
value "sb"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "ACHILLES"
)
(vvPair
variable "library"
value "uart_lib"
)
(vvPair
variable "mm"
value "08"
)
(vvPair
variable "module_name"
value "uarttop"
)
(vvPair
variable "month"
value "Aug"
)
(vvPair
variable "month_long"
value "August"
)
(vvPair
variable "p"
value "D:\\hdl_designs\\uart\\uart_lib\\hds\\uarttop\\symbol.sb"
)
(vvPair
variable "p_logical"
value "D:\\hdl_designs\\uart\\uart_lib\\hds\\uarttop\\symbol.sb"
)
(vvPair
variable "project_name"
value "uart"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "<TBD>"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "D:/PRODUCTS/PRECISIONSYNTHESIS2003/MGC_HOME/BIN"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "time"
value "12:44:04"
)
(vvPair
variable "unit"
value "uarttop"
)
(vvPair
variable "user"
value "Hans"
)
(vvPair
variable "version"
value "2003.1 (Build 399)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2003"
)
(vvPair
variable "yy"
value "03"
)
]
)
uid 51,0
optionalChildren [
*1 (SymbolBody
uid 8,0
optionalChildren [
*2 (CptPort
uid 52,0
ps "OnEdgeStrategy"
shape (Triangle
uid 53,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,6625,15000,7375"
)
n "clk"
t "std_logic"
o 1
r 1
tg (CPTG
uid 54,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 55,0
va (VaSet
)
xt "16000,6500,16900,7500"
st "clk"
blo "16000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 56,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2000,60000,2800"
st "clk     : IN     std_logic  ;
"
)
)
*3 (CptPort
uid 62,0
ps "OnEdgeStrategy"
shape (Triangle
uid 63,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,6625,33750,7375"
)
n "dbusout"
t "std_logic_vector"
b "(7 DOWNTO 0)"
m 1
o 4
r 2
tg (CPTG
uid 64,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 65,0
va (VaSet
)
xt "26400,6500,32000,7500"
st "dbusout : (7:0)"
ju 2
blo "32000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 66,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8400,70000,9200"
st "dbusout : OUT    std_logic_vector (7 DOWNTO 0) ;
"
)
)
*4 (CptPort
uid 67,0
ps "OnEdgeStrategy"
shape (Triangle
uid 68,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,8625,15000,9375"
)
n "rd"
t "std_logic"
o 2
r 3
tg (CPTG
uid 69,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 70,0
va (VaSet
)
xt "16000,8500,16700,9500"
st "rd"
blo "16000,9300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 71,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3600,60000,4400"
st "rd      : IN     std_logic  ;
"
)
)
*5 (CptPort
uid 72,0
ps "OnEdgeStrategy"
shape (Triangle
uid 73,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,9625,15000,10375"
)
n "resetn"
t "std_logic"
o 3
r 4
tg (CPTG
uid 74,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 75,0
va (VaSet
)
xt "16000,9500,18100,10500"
st "resetn"
blo "16000,10300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 76,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4400,60000,5200"
st "resetn  : IN     std_logic  ;
"
)
)
*6 (CptPort
uid 82,0
ps "OnEdgeStrategy"
shape (Triangle
uid 83,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,7625,33750,8375"
)
n "ferror"
t "std_logic"
m 1
o 5
r 5
tg (CPTG
uid 84,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 85,0
va (VaSet
)
xt "30100,7500,32000,8500"
st "ferror"
ju 2
blo "32000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 86,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9200,60000,10000"
st "ferror  : OUT    std_logic  ;
"
)
)
*7 (CptPort
uid 87,0
ps "OnEdgeStrategy"
shape (Triangle
uid 88,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,8625,33750,9375"
)
n "rdrf"
t "std_logic"
m 1
o 6
r 6
tg (CPTG
uid 89,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 90,0
va (VaSet
)
xt "30800,8500,32000,9500"
st "rdrf"
ju 2
blo "32000,9300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 91,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10000,60000,10800"
st "rdrf    : OUT    std_logic  ;
"
)
)
*8 (CptPort
uid 117,0
ps "OnEdgeStrategy"
shape (Triangle
uid 118,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,10625,15000,11375"
)
n "dbusin"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 7
r 7
tg (CPTG
uid 119,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 120,0
va (VaSet
)
xt "16000,10500,21200,11500"
st "dbusin : (7:0)"
blo "16000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 121,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2800,70000,3600"
st "dbusin  : IN     std_logic_vector (7 DOWNTO 0) ;
"
)
)
*9 (CptPort
uid 122,0
ps "OnEdgeStrategy"
shape (Triangle
uid 123,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,11625,15000,12375"
)
n "rx"
t "std_logic"
o 7
r 8
tg (CPTG
uid 124,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 125,0
va (VaSet
)
xt "16000,11500,16600,12500"
st "rx"
blo "16000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 126,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5200,60000,6000"
st "rx      : IN     std_logic  ;
"
)
)
*10 (CptPort
uid 127,0
ps "OnEdgeStrategy"
shape (Triangle
uid 128,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,12625,15000,13375"
)
n "rxclk16"
t "std_logic"
o 7
r 9
tg (CPTG
uid 129,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 130,0
va (VaSet
)
xt "16000,12500,18300,13500"
st "rxclk16"
blo "16000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 131,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6000,60000,6800"
st "rxclk16 : IN     std_logic  ;
"
)
)
*11 (CptPort
uid 132,0
ps "OnEdgeStrategy"
shape (Triangle
uid 133,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,9625,33750,10375"
)
n "tdre"
t "std_logic"
m 1
o 7
r 10
tg (CPTG
uid 134,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 135,0
va (VaSet
)
xt "30700,9500,32000,10500"
st "tdre"
ju 2
blo "32000,10300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 136,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10800,60000,11600"
st "tdre    : OUT    std_logic  ;
"
)
)
*12 (CptPort
uid 137,0
ps "OnEdgeStrategy"
shape (Triangle
uid 138,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,10625,33750,11375"
)
n "tx"
t "std_logic"
m 1
o 7
r 11
tg (CPTG
uid 139,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 140,0
va (VaSet
)
xt "31500,10500,32000,11500"
st "tx"
ju 2
blo "32000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 141,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,11600,59000,12400"
st "tx      : OUT    std_logic 
"
)
)
*13 (CptPort
uid 142,0
ps "OnEdgeStrategy"
shape (Triangle
uid 143,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,13625,15000,14375"
)
n "txclk"
t "std_logic"
o 7
r 12
tg (CPTG
uid 144,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 145,0
va (VaSet
)
xt "16000,13500,17400,14500"
st "txclk"
blo "16000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 146,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6800,60000,7600"
st "txclk   : IN     std_logic  ;
"
)
)
*14 (CptPort
uid 147,0
ps "OnEdgeStrategy"
shape (Triangle