symbol.sb

Modelsim FLI接口设计实例

DocumentHdrVersion "1.1"
Header (DocumentHdr
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
itemName "ALL"
)
]
)
version "16.1"
appVersion "2003.2 (Build 28)"
model (Symbol
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "D:\\HT86\\UART_LIB\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\HT86\\UART_LIB\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\HT86\\UART_LIB\\hds\\fli_socket\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\HT86\\UART_LIB\\hds\\fli_socket\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "D:\\HT86\\UART_LIB\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "config"
value "%(unit)_config"
)
(vvPair
variable "d"
value "D:\\HT86\\UART_LIB\\hds\\fli_socket"
)
(vvPair
variable "d_logical"
value "D:\\HT86\\UART_LIB\\hds\\fli_socket"
)
(vvPair
variable "date"
value "03/09/2003"
)
(vvPair
variable "day"
value "Wed"
)
(vvPair
variable "day_long"
value "Wednesday"
)
(vvPair
variable "dd"
value "03"
)
(vvPair
variable "entity_name"
value "fli_socket"
)
(vvPair
variable "ext"
value "sb"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "ACHILLES"
)
(vvPair
variable "library"
value "UART_FLI"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "D:/hdl_designs/uart/uart_lib/work/"
)
(vvPair
variable "mm"
value "09"
)
(vvPair
variable "module_name"
value "fli_socket"
)
(vvPair
variable "month"
value "Sep"
)
(vvPair
variable "month_long"
value "September"
)
(vvPair
variable "p"
value "D:\\HT86\\UART_LIB\\hds\\fli_socket\\symbol.sb"
)
(vvPair
variable "p_logical"
value "D:\\HT86\\UART_LIB\\hds\\fli_socket\\symbol.sb"
)
(vvPair
variable "project_name"
value "HT86"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "<TBD>"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "D:/PRODUCTS/PRECISIONSYNTHESIS2003/MGC_HOME/BIN"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "time"
value "17:32:25"
)
(vvPair
variable "unit"
value "fli_socket"
)
(vvPair
variable "user"
value "Hans"
)
(vvPair
variable "version"
value "2003.2 (Build 28)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2003"
)
(vvPair
variable "yy"
value "03"
)
]
)
uid 86,0
optionalChildren [
*1 (SymbolBody
uid 8,0
optionalChildren [
*2 (CptPort
uid 87,0
ps "OnEdgeStrategy"
shape (Triangle
uid 88,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,10625,25750,11375"
)
n "dbusin"
t "std_logic_vector"
b "(7 DOWNTO 0)"
m 1
o 9
r 6
tg (CPTG
uid 89,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 90,0
va (VaSet
)
xt "21800,10500,24000,11500"
st "dbusin"
ju 2
blo "24000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 91,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6000,70000,6800"
st "dbusin  : OUT    std_logic_vector (7 DOWNTO 0) ;"
)
)
*3 (CptPort
uid 92,0
ps "OnEdgeStrategy"
shape (Triangle
uid 93,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,17625,25750,18375"
)
n "dbusout"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 10
r 2
tg (CPTG
uid 94,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 95,0
va (VaSet
)
xt "21400,17500,24000,18500"
st "dbusout"
ju 2
blo "24000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 96,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2800,70000,3600"
st "dbusout : IN     std_logic_vector (7 DOWNTO 0) ;"
)
)
*4 (CptPort
uid 97,0
ps "OnEdgeStrategy"
shape (Triangle
uid 98,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,15625,25750,16375"
)
n "rd"
t "std_logic"
m 1
o 8
r 7
tg (CPTG
uid 99,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 100,0
va (VaSet
)
xt "23300,15500,24000,16500"
st "rd"
ju 2
blo "24000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 101,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6800,60000,7600"
st "rd      : OUT    std_logic  ;"
)
)
*5 (CptPort
uid 102,0
ps "OnEdgeStrategy"
shape (Triangle
uid 103,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,13625,25750,14375"
)
n "rdrf"
t "std_logic"
o 7
r 3
tg (CPTG
uid 104,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 105,0
va (VaSet
)
xt "22800,13500,24000,14500"
st "rdrf"
ju 2
blo "24000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 106,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3600,60000,4400"
st "rdrf    : IN     std_logic  ;"
)
)
*6 (CptPort
uid 107,0
ps "OnEdgeStrategy"
shape (Triangle
uid 108,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "19625,5250,20375,6000"
)
n "resetn"
t "std_logic"
o 11
r 4
tg (CPTG
uid 109,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 110,0
ro 270
va (VaSet
)
xt "19500,7000,20500,9100"
st "resetn"
ju 2
blo "20300,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 111,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4400,60000,5200"
st "resetn  : IN     std_logic  ;"
)
)
*7 (CptPort
uid 112,0
ps "OnEdgeStrategy"
shape (Triangle
uid 113,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,6625,25750,7375"
)
n "tdre"
t "std_logic"
o 5
r 5
tg (CPTG
uid 114,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 115,0
va (VaSet
)
xt "22700,6500,24000,7500"
st "tdre"
ju 2
blo "24000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 116,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5200,60000,6000"
st "tdre    : IN     std_logic  ;"
)
)
*8 (CptPort
uid 117,0
ps "OnEdgeStrategy"
shape (Triangle
uid 118,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,8625,25750,9375"
)
n "wr"
t "std_logic"
m 1
o 6
r 8
tg (CPTG
uid 119,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 120,0
va (VaSet
)
xt "23200,8500,24000,9500"
st "wr"
ju 2
blo "24000,9300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 121,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7600,59000,8400"
st "wr      : OUT    std_logic "
)
)
*9 (CptPort
uid 122,0
ps "OnEdgeStrategy"
shape (Triangle
uid 123,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,6625,15000,7375"
)
n "clk"
t "std_logic"
o 14
r 1
tg (CPTG
uid 124,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 125,0
va (VaSet
)
xt "16000,6500,16900,7500"
st "clk"
blo "16000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 126,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2000,60000,2800"
st "clk     : IN     std_logic  ;"
)
)
]
shape (Rectangle
uid 9,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,25000,19000"
)
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Arial,8,1"
)
xt "17850,11500,21650,12500"
st "UART_FLI"
blo "17850,12300"
)
second (Text
uid 12,0
va (VaSet
font "Arial,8,1"
)
xt "17850,12500,22150,13500"
st "fli_socket"
blo "17850,13300"
)
)
gi *10 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "-4000,8500,-4000,8500"
)
header "Generic Declarations"
)
elements [
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sTC 0
sF 0
)
portVis (PortSigDisplay
sTC 0
sF 0
)
)
*11 (Grouping
uid 16,0
optionalChildren [
*12 (CommentText