struct.bd

Modelsim FLI接口设计实例

]
)
ga (GenericAssociation
uid 265,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 266,0
text (MLText
uid 267,0
va (VaSet
font "Courier New,8,0"
)
xt "47000,31200,62000,32000"
st "PERIOD = 40 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "PERIOD"
type "time"
value "40 ns"
)
]
)
connectByName 1
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*29 (SaComponent
uid 272,0
optionalChildren [
*30 (CptPort
uid 282,0
ps "OnEdgeStrategy"
shape (Triangle
uid 283,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "50250,27625,51000,28375"
)
n "clk"
t "std_logic"
m 1
o 6
r 1
tg (CPTG
uid 284,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 285,0
va (VaSet
)
xt "52000,27500,52900,28500"
st "clk"
blo "52000,28300"
)
)
)
]
shape (Circle
uid 273,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "51000,26000,55000,30000"
radius 2000
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 274,0
optionalChildren [
*31 (Text
uid 278,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "55941,28575,59741,29575"
st "behaviour"
blo "55941,29375"
tm "SaCptArchNameMgr"
)
]
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*32 (Text
uid 275,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "55941,25575,59741,26575"
st "UART_FLI"
blo "55941,26375"
)
*33 (Text
uid 276,0
va (VaSet
font "Arial,8,1"
)
xt "55941,26575,58341,27575"
st "clkgen"
blo "55941,27375"
)
*34 (Text
uid 277,0
va (VaSet
font "Arial,8,1"
)
xt "55941,27575,56541,28575"
st "I4"
blo "55941,28375"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 279,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 280,0
text (MLText
uid 281,0
va (VaSet
font "Courier New,8,0"
)
xt "47000,25200,66500,26000"
st "PERIOD = 1.627604166 us    ( time ) "
)
header ""
)
elements [
(GiElement
name "PERIOD"
type "time"
value "1.627604166 us"
)
]
)
portVis (PortSigDisplay
sTC 0
sF 0
)
archName "behaviour"
archType 2
archFileType "VHDL_TEXT"
)
*35 (SaComponent
uid 286,0
optionalChildren [
*36 (CptPort
uid 296,0
ps "OnEdgeStrategy"
shape (Triangle
uid 297,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "50250,21625,51000,22375"
)
n "clk"
t "std_logic"
m 1
o 6
r 1
tg (CPTG
uid 298,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 299,0
va (VaSet
)
xt "52000,21500,52900,22500"
st "clk"
blo "52000,22300"
)
)
)
]
shape (Circle
uid 287,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "51000,20000,55000,24000"
radius 2000
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 288,0
optionalChildren [
*37 (Text
uid 292,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "55855,22514,59655,23514"
st "behaviour"
blo "55855,23314"
tm "SaCptArchNameMgr"
)
]
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*38 (Text
uid 289,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "55855,19514,59655,20514"
st "UART_FLI"
blo "55855,20314"
)
*39 (Text
uid 290,0
va (VaSet
font "Arial,8,1"
)
xt "55855,20514,58255,21514"
st "clkgen"
blo "55855,21314"
)
*40 (Text
uid 291,0
va (VaSet
font "Arial,8,1"
)
xt "55855,21514,56455,22514"
st "I5"
blo "55855,22314"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 293,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 294,0
text (MLText
uid 295,0
va (VaSet
font "Courier New,8,0"
)
xt "47000,19200,68000,20000"
st "PERIOD = 0.101725260375 us    ( time ) "
)
header ""
)
elements [
(GiElement
name "PERIOD"
type "time"
value "0.101725260375 us"
)
]
)
portVis (PortSigDisplay
sTC 0
sF 0
)
archName "behaviour"
archType 2
archFileType "VHDL_TEXT"
)
*41 (SaComponent
uid 329,0
optionalChildren [
*42 (CptPort
uid 338,0
ps "OnEdgeStrategy"
shape (Triangle
uid 339,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18000,16625,18750,17375"
)
n "async_reset"
t "std_logic"
m 1
o 2
r 2
tg (CPTG
uid 340,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 341,0
va (VaSet
)
xt "12200,16500,17000,17500"
st "async_reset"
ju 2
blo "17000,17300"
)
)
)
*43 (CptPort
uid 342,0
ps "OnEdgeStrategy"
shape (Triangle
uid 343,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18000,17625,18750,18375"
)
n "async_resetn"
t "std_logic"
m 1
o 3
r 3
tg (CPTG
uid 344,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 345,0
va (VaSet
)
xt "11800,17500,17000,18500"
st "async_resetn"
ju 2
blo "17000,18300"
)
)
)
*44 (CptPort
uid 346,0
ps "OnEdgeStrategy"
shape (Triangle
uid 347,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "7250,13625,8000,14375"
)
n "clk"
t "std_logic"
o 1
r 1
tg (CPTG
uid 348,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 349,0
va (VaSet
)
xt "9000,13500,9900,14500"
st "clk"
blo "9000,14300"
)
)
)
*45 (CptPort
uid 350,0
ps "OnEdgeStrategy"
shape (Triangle
uid 351,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18000,13625,18750,14375"
)
n "sync_reset"
t "std_logic"
m 1
o 4
r 4
tg (CPTG
uid 352,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 353,0
va (VaSet
)
xt "12600,13500,17000,14500"
st "sync_reset"
ju 2
blo "17000,14300"
)
)
)
*46 (CptPort
uid 354,0
ps "OnEdgeStrategy"
shape (Triangle
uid 355,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18000,14625,18750,15375"
)
n "sync_resetn"
t "std_logic"
m 1
o 5
r 5
tg (CPTG
uid 356,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 357,0
va (VaSet
)
xt "12200,14500,17000,15500"
st "sync_resetn"
ju 2
blo "17000,15300"
)
)
)
]
shape (Rectangle
uid 330,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "8000,13000,18000,19000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 331,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*47 (Text
uid 332,0
va (VaSet
font "Arial,8,1"
)
xt "8400,15000,12200,16000"
st "UART_FLI"
blo "8400,15800"
)
*48 (Text
uid 333,0
va (VaSet
font "Arial,8,1"
)
xt "8400,16000,11600,17000"
st "resetgen"
blo "8400,16800"
)
*49 (Text
uid 334,0
va (VaSet
font "Arial,8,1"
)
xt "8400,17000,9000,18000"
st "I2"
blo "8400,17800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 335,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 336,0
text (MLText
uid 337,0
va (VaSet
font "Courier New,8,0"
)
xt "6000,10400,24000,12000"
st "SYNCDEL  = 12        ( integer ) 
ASYNCDEL = 132 ns    ( time    ) "
)
header ""
)
elements [
(GiElement
name "SYNCDEL"
type "integer"
value "12"
)
(GiElement
name "ASYNCDEL"
type "time"
value "132 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*50 (Net
uid 390,0
name "clk"
type "std_logic"
orderNo 5
declText (MLText
uid 391,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,3000,36500,3800"
st "SIGNAL clk     : std_logic"
)
)
*51 (Net
uid 402,0
name "resetn"
type "std_logic"
orderNo 5
declText (MLText
uid 403,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,3800,36500,4600"
st "SIGNAL resetn  : std_logic"
)
)
*52 (Net
uid 426,0
name "rxclk16"
type "std_logic"
orderNo 4
declText (MLText
uid 427,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,5400,36500,6200"
st "SIGNAL rxclk16 : std_logic"
)
)
*53 (Net
uid 428,0
name "txclk"
type "std_logic"
orderNo 5
declText (MLText
uid 429,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,6200,36500,7000"
st "SIGNAL txclk   : std_logic"
)
)
*54 (Wire
uid 304,0
optionalChildren [
*55 (CommentText
uid 312,0
ps "EdgeToEdgeStrategy"
shape (Rectangle
uid 313,0
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "41000,14000,45000,16000"
)
oxt "0,0,15000,5000"
text (MLText
uid 314,0
va (VaSet
fg "0,0,32768"
)
xt "41200,14200,44300,15200"
st "
Loopback
"
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 4000
)
included 1
)
]
shape (OrthoPolyLine
uid 305,0
va (VaSet
vasetType 3
lineColor "65535,0,0"
lineWidth 2
)
xt "37750,17000,42000,19000"
pts [
"37750,19000"
"42000,19000"
"42000,17000"
"37750,17000"
]
)
start &6
end &8
es 0
sat 32
eat 32
st 0
si 0
tg (WTG
uid 310,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 311,0
va (VaSet
isHidden 1
)
xt "39750,25000,40350,26000"
st "rx"
blo "39750,25800"
tm "WireNameMgr"
)
)
on &1
)
*56 (Wire
uid 392,0
shape (OrthoPolyLine
uid 393,0
va (VaSet
vasetType 3
)
xt "37750,34000,50250,34000"
pts [
"50250,34000"
"37750,34000"
]
)
start &25
end &3
sat 32
eat 32
st 0
si 0
tg (WTG
uid 394,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 395,0
va (VaSet
)
xt "47000,33000,47900,34000"
st "clk"
blo "47000,33800"
tm "WireNameMgr"
)
)
on &50
)
*57 (Wire
uid 398,0
shape (OrthoPolyLine
uid 399,0
va (VaSet
vasetType 3
)
xt "18750,18000,22250,18000"
pts [
"18750,18000"
"22250,18000"
]
)
start &43
end &5
sat 32
eat 32
st 0
si 0
tg (WTG
uid 400,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 401,0
va (VaSet
)
xt "19000,17000,21100,18000"
st "resetn"
blo "19000,17800"
tm "WireNameMgr"
)
)
on &51
)
*58 (Wire
uid 406,0
shape (OrthoPolyLine
uid 407,0
va (VaSet
vasetType 3
)
xt "5000,14000,7250,14000"
pts [
"5000,14000"
"7250,14000"
]
)
end &44
sat 16
eat 32
st 0
si 0
tg (WTG
uid 410,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 411,0
va (VaSet
)
xt "6000,13000,6900,14000"
st "clk"
blo "6000,13800"
tm "WireNameMgr"
)
)
on &50
)
*59 (Wire
uid 416,0
shape (OrthoPolyLine
uid 417,0
va (VaSet
vasetType 3
)
xt "37750,22000,50250,22000"
pts [
"50250,22000"
"37750,22000"
]
)
start &36
end &7
sat 32
eat 32
st 0
si 0
tg (WTG
uid 418,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 419,0
va (VaSet
)
xt "47000,21000,49300,22000"
st "rxclk16"
blo "47000,21800"
tm "WireNameMgr"
)
)
on &52
)
*60 (Wire
uid 422,0
shape (OrthoPolyLine
uid 423,0
va (VaSet
vasetType 3
)
xt "37750,28000,50250,28000"
pts [
"50250,28000"
"37750,28000"
]
)
start &30
end &9
sat 32
eat 32
st 0
si 0
tg (WTG
uid 424,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 425,0
va (VaSet
)
xt "47000,27000,48400,28000"
st "txclk"
blo "47000,27800"
tm "WireNameMgr"
)
)
on &53
)
]
LanguageMgr "VhdlLangMgr"
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *61 (PackageList
uid 202,0
stg "VerticalLayoutStrategy"
textVec [
*62 (Text
uid 203,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*63 (MLText
uid 204,0
va (VaSet
)
xt "0,1000,11400,3000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 205,0
stg "VerticalLayoutStrategy"
textVec [
*64 (Text
uid 206,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*65 (Text
uid 207,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*66 (MLText
uid 208,0
va (VaSet
isHidden 1
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*67 (Text
uid 209,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*68 (MLText
uid 210,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*69 (Text
uid 211,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,5000,29900,6000"
st "End-module directives:"
blo "20000,5800"
)
*70 (MLText
uid 212,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "-4,-4,1397,1026"
viewArea "-1100,-1100,81738,50201"
cachedDiagramExtent "0,0,73000,49000"
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 435,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,1600,1200"
st "
Text
"
tm "CommentText"
wrapOption 3