struct.bd

Modelsim FLI接口设计实例

DocumentHdrVersion "1.1"
Header (DocumentHdr
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
itemName "ALL"
)
]
instances [
(Instance
name "I0"
duLibraryName "UART_FLI"
duName "uart_fli_top"
elements [
]
mwi 0
uid 161,0
)
(Instance
name "I3"
duLibraryName "UART_FLI"
duName "clkgen"
elements [
(GiElement
name "PERIOD"
type "time"
value "40 ns"
)
]
mwi 0
uid 259,0
)
(Instance
name "I4"
duLibraryName "UART_FLI"
duName "clkgen"
archName "behaviour"
archFileType 9
elements [
(GiElement
name "PERIOD"
type "time"
value "1.627604166 us"
)
]
mwi 0
uid 272,0
)
(Instance
name "I5"
duLibraryName "UART_FLI"
duName "clkgen"
archName "behaviour"
archFileType 9
elements [
(GiElement
name "PERIOD"
type "time"
value "0.101725260375 us"
)
]
mwi 0
uid 286,0
)
(Instance
name "I2"
duLibraryName "UART_FLI"
duName "resetgen"
elements [
(GiElement
name "SYNCDEL"
type "integer"
value "12"
)
(GiElement
name "ASYNCDEL"
type "time"
value "132 ns"
)
]
mwi 0
uid 329,0
)
]
)
version "21.1"
appVersion "2003.2 (Build 28)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "D:\\HT86\\UART_FLI\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\HT86\\UART_FLI\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top_tb\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top_tb\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "D:\\HT86\\UART_FLI\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "config"
value "%(unit)_config"
)
(vvPair
variable "d"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top_tb"
)
(vvPair
variable "d_logical"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top_tb"
)
(vvPair
variable "date"
value "13/09/2003"
)
(vvPair
variable "day"
value "Sat"
)
(vvPair
variable "day_long"
value "Saturday"
)
(vvPair
variable "dd"
value "13"
)
(vvPair
variable "entity_name"
value "uart_fli_top_tb"
)
(vvPair
variable "ext"
value "bd"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "ACHILLES"
)
(vvPair
variable "library"
value "UART_FLI"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "D:/HT86/UART_FLI/work/"
)
(vvPair
variable "mm"
value "09"
)
(vvPair
variable "module_name"
value "uart_fli_top_tb"
)
(vvPair
variable "month"
value "Sep"
)
(vvPair
variable "month_long"
value "September"
)
(vvPair
variable "p"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top_tb\\struct.bd"
)
(vvPair
variable "p_logical"
value "D:\\HT86\\UART_FLI\\hds\\uart_fli_top_tb\\struct.bd"
)
(vvPair
variable "project_name"
value "HT86"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "<TBD>"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "D:/PRODUCTS/PRECISIONSYNTHESIS2003/MGC_HOME/BIN"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "time"
value "10:10:09"
)
(vvPair
variable "unit"
value "uart_fli_top_tb"
)
(vvPair
variable "user"
value "Hans"
)
(vvPair
variable "version"
value "2003.2 (Build 28)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2003"
)
(vvPair
variable "yy"
value "03"
)
]
)
uid 213,0
optionalChildren [
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orderNo 5
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xt "22000,4600,36500,5400"
st "SIGNAL rx      : std_logic"
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optionalChildren [
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shape (Triangle
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ro 270
va (VaSet
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fg "0,65535,0"
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xt "37000,33625,37750,34375"
)
n "clk"
t "std_logic"
o 1
r 1
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "35100,33500,36000,34500"
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blo "36000,34300"
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n "ferror"
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m 1
o 1
r 2
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ps "CptPortTextPlaceStrategy"
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f (Text
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va (VaSet
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)
)
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ps "OnEdgeStrategy"
shape (Triangle
uid 18,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "22250,17625,23000,18375"
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n "resetn"
t "std_logic"
o 1
r 3
tg (CPTG
uid 19,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "24000,17500,26100,18500"
st "resetn"
blo "24000,18300"
)
)
)
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ps "OnEdgeStrategy"
shape (Triangle
uid 22,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,18625,37750,19375"
)
n "rx"
t "std_logic"
o 1
r 4
tg (CPTG
uid 23,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 24,0
va (VaSet
)
xt "35400,18500,36000,19500"
st "rx"
ju 2
blo "36000,19300"
)
)
)
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uid 25,0
ps "OnEdgeStrategy"
shape (Triangle
uid 26,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,21625,37750,22375"
)
n "rxclk16"
t "std_logic"
o 1
r 5
tg (CPTG
uid 27,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 28,0
va (VaSet
)
xt "33700,21500,36000,22500"
st "rxclk16"
ju 2
blo "36000,22300"
)
)
)
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uid 29,0
ps "OnEdgeStrategy"
shape (Triangle
uid 30,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,16625,37750,17375"
)
n "tx"
t "std_logic"
m 1
o 1
r 6
tg (CPTG
uid 31,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 32,0
va (VaSet
)
xt "35500,16500,36000,17500"
st "tx"
ju 2
blo "36000,17300"
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)
)
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uid 33,0
ps "OnEdgeStrategy"
shape (Triangle
uid 34,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,27625,37750,28375"
)
n "txclk"
t "std_logic"
o 1
r 7
tg (CPTG
uid 35,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 36,0
va (VaSet
)
xt "34600,27500,36000,28500"
st "txclk"
ju 2
blo "36000,28300"
)
)
)
]
shape (Rectangle
uid 162,0
va (VaSet
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fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
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xt "23000,15000,37000,36000"
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oxt "15000,11000,33000,31000"
ttg (MlTextGroup
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ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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va (VaSet
font "Arial,8,1"
)
xt "24400,31000,28200,32000"
st "UART_FLI"
blo "24400,31800"
)
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uid 165,0
va (VaSet
font "Arial,8,1"
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xt "24400,32000,29500,33000"
st "uart_fli_top"
blo "24400,32800"
)
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va (VaSet
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xt "24400,33000,25000,34000"
st "I0"
blo "24400,33800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
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text (MLText
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font "Courier New,8,0"
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xt "4000,9000,4000,9000"
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elements [
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)
portVis (PortSigDisplay
sIVOD 1
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archFileType "UNKNOWN"
)
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optionalChildren [
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xt "36000,48000,53000,49000"
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text (MLText
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xt "36200,48000,45400,49000"
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xt "53200,44000,55800,45000"
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text (MLText
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xt "32200,46000,33900,47000"
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tm "CommentText"
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text (MLText
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shape (Triangle
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n "clk"
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r 1
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f (Text
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