prev_cmp_i2c_eeprom.map.qmsg

VHDL语言写的IIC实现EEPROM

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 15 16:19:07 2008 " "Info: Processing started: Mon Dec 15 16:19:07 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off I2c_eeprom -c I2c_eeprom " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off I2c_eeprom -c I2c_eeprom" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2c_eeprom.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2c_eeprom.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 I2c_eeprom " "Info: Found entity 1: I2c_eeprom" {  } { { "I2c_eeprom.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/EEPROM/I2c_eeprom.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "I2c_eeprom " "Info: Elaborating entity \"I2c_eeprom\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "hc164_driver.v 1 1 " "Warning: Using design file hc164_driver.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 hc164_driver " "Info: Found entity 1: hc164_driver" {  } { { "hc164_driver.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/hc164_driver.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hc164_driver hc164_driver:inst1 " "Info: Elaborating entity \"hc164_driver\" for hierarchy \"hc164_driver:inst1\"" {  } { { "I2c_eeprom.bdf" "inst1" { Schematic "C:/Documents and Settings/Administrator/桌面/EEPROM/I2c_eeprom.bdf" { { 272 776 944 400 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "data_rep packed i2c_top.v(16) " "Warning (10227): Verilog HDL Port Declaration warning at i2c_top.v(16): data type declaration for \"data_rep\" declares packed dimensions but the port declaration declaration does not" {  } { { "i2c_top.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_top.v" 16 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "data_rep i2c_top.v(27) " "Info (10151): Verilog HDL Declaration information at i2c_top.v(27): \"data_rep\" is declared here" {  } { { "i2c_top.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_top.v" 27 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "i2c_top.v 1 1 " "Warning: Using design file i2c_top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_top " "Info: Found entity 1: i2c_top" {  } { { "i2c_top.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_top.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_top i2c_top:inst " "Info: Elaborating entity \"i2c_top\" for hierarchy \"i2c_top:inst\"" {  } { { "I2c_eeprom.bdf" "inst" { Schematic "C:/Documents and Settings/Administrator/桌面/EEPROM/I2c_eeprom.bdf" { { 184 248 400 280 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "i2c_wr.v 1 1 " "Warning: Using design file i2c_wr.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_wr " "Info: Found entity 1: i2c_wr" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_wr i2c_top:inst\|i2c_wr:i2c_wr_inst " "Info: Elaborating entity \"i2c_wr\" for hierarchy \"i2c_top:inst\|i2c_wr:i2c_wr_inst\"" {  } { { "i2c_top.v" "i2c_wr_inst" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_top.v" 204 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_wr.v(110) " "Warning (10230): Verilog HDL assignment warning at i2c_wr.v(110): truncated value with size 32 to match size of target (1)" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_wr.v(111) " "Warning (10230): Verilog HDL assignment warning at i2c_wr.v(111): truncated value with size 32 to match size of target (1)" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}