prev_cmp_i2c_eeprom.fit.qmsg

VHDL语言写的IIC实现EEPROM

{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 6 " "Warning: No exact pin location assignment(s) for 1 pins of 6 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pld_CLEAR_n " "Info: Pin pld_CLEAR_n not assigned to an exact location on the device" {  } { { "I2c_eeprom.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/EEPROM/I2c_eeprom.bdf" { { 224 -48 120 240 "pld_CLEAR_n" "" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pld_CLEAR_n } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pld_CLEAR_n } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk1 (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk1 (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|clk_div " "Info: Destination node i2c_top:inst\|clk_div" {  } { { "i2c_top.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_top.v" 44 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|clk_div } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|clk_div } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "I2c_eeprom.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/EEPROM/I2c_eeprom.bdf" { { 208 -48 120 224 "clk1" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "i2c_top:inst\|clk_div  " "Info: Automatically promoted node i2c_top:inst\|clk_div " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|clk_div~43 " "Info: Destination node i2c_top:inst\|clk_div~43" {  } { { "i2c_top.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_top.v" 44 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|clk_div~43 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|clk_div~43 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "i2c_top.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_top.v" 44 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|clk_div } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|clk_div } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pld_CLEAR_n (placed in PIN 24 (CLK1, LVDSCLK0n, Input)) " "Info: Automatically promoted node pld_CLEAR_n (placed in PIN 24 (CLK1, LVDSCLK0n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\]~716 " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\]~716" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 268 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~716 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~716 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_buf\[1\] " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_buf\[1\]" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 268 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_buf[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_buf[1] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8in_state.sh8in_bit5~121 " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8in_state.sh8in_bit5~121" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 31 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit5~121 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit5~121 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|head_state.head_bit " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|head_state.head_bit" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 32 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|head_state.head_bit } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|head_state.head_bit } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_end " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_end" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 33 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_end } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_end } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8in_state.sh8in_bit7~67 " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8in_state.sh8in_bit7~67" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 31 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit7~67 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit7~67 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_bit " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_bit" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 33 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_buf\[0\] " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_buf\[0\]" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 268 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_buf[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_buf[0] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_buf\[7\]~567 " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_buf\[7\]~567" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 268 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7]~567 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7]~567 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_state.sh8out_bit6 " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_state.sh8out_bit6" {  } { { "i2c_wr.v" "" { Text "C:/Documents and Settings/Administrator/桌面/EEPROM/i2c_wr.v" 30 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit6 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit6 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "I2c_eeprom.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/EEPROM/I2c_eeprom.bdf" { { 224 -48 120 240 "pld_CLEAR_n" "" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pld_CLEAR_n } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pld_CLEAR_n } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}