ff.tan.qmsg

QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register lift:inst2\|ladd\[0\] register lift:inst2\|liftor\[2\] 10.68 MHz 93.6 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 10.68 MHz between source register \"lift:inst2\|ladd\[0\]\" and destination register \"lift:inst2\|liftor\[2\]\" (period= 93.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.600 ns + Longest register register " "Info: + Longest register to register delay is 6.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lift:inst2\|ladd\[0\] 1 REG LC1_H47 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_H47; Fanout = 6; REG Node = 'lift:inst2\|ladd\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lift:inst2|ladd[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.600 ns) 2.000 ns lift:inst2\|liftor~496 2 COMB LC5_H47 1 " "Info: 2: + IC(0.400 ns) + CELL(1.600 ns) = 2.000 ns; Loc. = LC5_H47; Fanout = 1; COMB Node = 'lift:inst2\|liftor~496'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { lift:inst2|ladd[0] lift:inst2|liftor~496 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.200 ns) 3.600 ns lift:inst2\|liftor~509 3 COMB LC3_H47 1 " "Info: 3: + IC(0.400 ns) + CELL(1.200 ns) = 3.600 ns; Loc. = LC3_H47; Fanout = 1; COMB Node = 'lift:inst2\|liftor~509'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { lift:inst2|liftor~496 lift:inst2|liftor~509 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 5.000 ns lift:inst2\|liftor~500 4 COMB LC4_H47 1 " "Info: 4: + IC(0.000 ns) + CELL(1.400 ns) = 5.000 ns; Loc. = LC4_H47; Fanout = 1; COMB Node = 'lift:inst2\|liftor~500'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { lift:inst2|liftor~509 lift:inst2|liftor~500 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.200 ns) 6.600 ns lift:inst2\|liftor\[2\] 5 REG LC2_H47 21 " "Info: 5: + IC(0.400 ns) + CELL(1.200 ns) = 6.600 ns; Loc. = LC2_H47; Fanout = 21; REG Node = 'lift:inst2\|liftor\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { lift:inst2|liftor~500 lift:inst2|liftor[2] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.400 ns ( 81.82 % ) " "Info: Total cell delay = 5.400 ns ( 81.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 18.18 % ) " "Info: Total interconnect delay = 1.200 ns ( 18.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.600 ns" { lift:inst2|ladd[0] lift:inst2|liftor~496 lift:inst2|liftor~509 lift:inst2|liftor~500 lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.600 ns" { lift:inst2|ladd[0] {} lift:inst2|liftor~496 {} lift:inst2|liftor~509 {} lift:inst2|liftor~500 {} lift:inst2|liftor[2] {} } { 0.000ns 0.400ns 0.400ns 0.000ns 0.400ns } { 0.000ns 1.600ns 1.200ns 1.400ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-38.300 ns - Smallest " "Info: - Smallest clock skew is -38.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 13.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 13.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkin 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 64 -32 136 80 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.900 ns) 5.800 ns lift:inst2\|dir\[0\] 2 REG LC1_H37 29 " "Info: 2: + IC(2.900 ns) + CELL(0.900 ns) = 5.800 ns; Loc. = LC1_H37; Fanout = 29; REG Node = 'lift:inst2\|dir\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { clkin lift:inst2|dir[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.100 ns) + CELL(0.000 ns) 13.900 ns lift:inst2\|liftor\[2\] 3 REG LC2_H47 21 " "Info: 3: + IC(8.100 ns) + CELL(0.000 ns) = 13.900 ns; Loc. = LC2_H47; Fanout = 21; REG Node = 'lift:inst2\|liftor\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.100 ns" { lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 20.86 % ) " "Info: Total cell delay = 2.900 ns ( 20.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.000 ns ( 79.14 % ) " "Info: Total interconnect delay = 11.000 ns ( 79.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.900 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.900 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[2] {} } { 0.000ns 0.000ns 2.900ns 8.100ns } { 0.000ns 2.000ns 0.900ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 52.200 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 52.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkin 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 64 -32 136 80 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.900 ns) 5.800 ns lift:inst2\|dir\[0\] 2 REG LC1_H37 29 " "Info: 2: + IC(2.900 ns) + CELL(0.900 ns) = 5.800 ns; Loc. = LC1_H37; Fanout = 29; REG Node = 'lift:inst2\|dir\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { clkin lift:inst2|dir[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.100 ns) + CELL(0.900 ns) 14.800 ns lift:inst2\|liftor\[0\] 3 REG LC2_H48 33 " "Info: 3: + IC(8.100 ns) + CELL(0.900 ns) = 14.800 ns; Loc. = LC2_H48; Fanout = 33; REG Node = 'lift:inst2\|liftor\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { lift:inst2|dir[0] lift:inst2|liftor[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.200 ns) + CELL(1.700 ns) 20.700 ns lift:inst2\|p2~853 4 COMB LC5_H33 1 " "Info: 4: + IC(4.200 ns) + CELL(1.700 ns) = 20.700 ns; Loc. = LC5_H33; Fanout = 1; COMB Node = 'lift:inst2\|p2~853'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { lift:inst2|liftor[0] lift:inst2|p2~853 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.700 ns) 22.800 ns lift:inst2\|p2~854 5 COMB LC6_H33 1 " "Info: 5: + IC(0.400 ns) + CELL(1.700 ns) = 22.800 ns; Loc. = LC6_H33; Fanout = 1; COMB Node = 'lift:inst2\|p2~854'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lift:inst2|p2~853 lift:inst2|p2~854 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.700 ns) 24.900 ns lift:inst2\|p2~855 6 COMB LC4_H33 15 " "Info: 6: + IC(0.400 ns) + CELL(1.700 ns) = 24.900 ns; Loc. = LC4_H33; Fanout = 15; COMB Node = 'lift:inst2\|p2~855'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lift:inst2|p2~854 lift:inst2|p2~855 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(1.300 ns) 30.100 ns lift:inst2\|dr\[2\]~593 7 COMB LC2_H45 1 " "Info: 7: + IC(3.900 ns) + CELL(1.300 ns) = 30.100 ns; Loc. = LC2_H45; Fanout = 1; COMB Node = 'lift:inst2\|dr\[2\]~593'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { lift:inst2|p2~855 lift:inst2|dr[2]~593 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 31.500 ns lift:inst2\|dr\[2\]~572 8 COMB LC3_H45 1 " "Info: 8: + IC(0.000 ns) + CELL(1.400 ns) = 31.500 ns; Loc. = LC3_H45; Fanout = 1; COMB Node = 'lift:inst2\|dr\[2\]~572'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { lift:inst2|dr[2]~593 lift:inst2|dr[2]~572 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.700 ns) 33.600 ns lift:inst2\|dr\[2\] 9 REG LC8_H45 1 " "Info: 9: + IC(0.400 ns) + CELL(1.700 ns) = 33.600 ns; Loc. = LC8_H45; Fanout = 1; REG Node = 'lift:inst2\|dr\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lift:inst2|dr[2]~572 lift:inst2|dr[2] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.600 ns) 35.600 ns lift:inst2\|p3~1 10 COMB LC1_H45 4 " "Info: 10: + IC(0.400 ns) + CELL(1.600 ns) = 35.600 ns; Loc. = LC1_H45; Fanout = 4; COMB Node = 'lift:inst2\|p3~1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { lift:inst2|dr[2] lift:inst2|p3~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.700 ns) 39.400 ns lift:inst2\|Mux2~270 11 COMB LC6_H44 1 " "Info: 11: + IC(2.100 ns) + CELL(1.700 ns) = 39.400 ns; Loc. = LC6_H44; Fanout = 1; COMB Node = 'lift:inst2\|Mux2~270'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { lift:inst2|p3~1 lift:inst2|Mux2~270 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.700 ns) 41.500 ns lift:inst2\|Mux2~271 12 COMB LC8_H44 1 " "Info: 12: + IC(0.400 ns) + CELL(1.700 ns) = 41.500 ns; Loc. = LC8_H44; Fanout = 1; COMB Node = 'lift:inst2\|Mux2~271'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lift:inst2|Mux2~270 lift:inst2|Mux2~271 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.200 ns) 43.100 ns lift:inst2\|Mux2~281 13 COMB LC3_H44 1 " "Info: 13: + IC(0.400 ns) + CELL(1.200 ns) = 43.100 ns; Loc. = LC3_H44; Fanout = 1; COMB Node = 'lift:inst2\|Mux2~281'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { lift:inst2|Mux2~271 lift:inst2|Mux2~281 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 44.500 ns lift:inst2\|Mux2~276 14 COMB LC4_H44 2 " "Info: 14: + IC(0.000 ns) + CELL(1.400 ns) = 44.500 ns; Loc. = LC4_H44; Fanout = 2; COMB Node = 'lift:inst2\|Mux2~276'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { lift:inst2|Mux2~281 lift:inst2|Mux2~276 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.700 ns) 48.500 ns lift:inst2\|ladd\[0\]~87 15 COMB LC5_H49 1 " "Info: 15: + IC(2.300 ns) + CELL(1.700 ns) = 48.500 ns; Loc. = LC5_H49; Fanout = 1; COMB Node = 'lift:inst2\|ladd\[0\]~87'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { lift:inst2|Mux2~276 lift:inst2|ladd[0]~87 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.700 ns) 52.200 ns lift:inst2\|ladd\[0\] 16 REG LC1_H47 6 " "Info: 16: + IC(2.000 ns) + CELL(1.700 ns) = 52.200 ns; Loc. = LC1_H47; Fanout = 6; REG Node = 'lift:inst2\|ladd\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { lift:inst2|ladd[0]~87 lift:inst2|ladd[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "24.300 ns ( 46.55 % ) " "Info: Total cell delay = 24.300 ns ( 46.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "27.900 ns ( 53.45 % ) " "Info: Total interconnect delay = 27.900 ns ( 53.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "52.200 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[0] lift:inst2|p2~853 lift:inst2|p2~854 lift:inst2|p2~855 lift:inst2|dr[2]~593 lift:inst2|dr[2]~572 lift:inst2|dr[2] lift:inst2|p3~1 lift:inst2|Mux2~270 lift:inst2|Mux2~271 lift:inst2|Mux2~281 lift:inst2|Mux2~276 lift:inst2|ladd[0]~87 lift:inst2|ladd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "52.200 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[0] {} lift:inst2|p2~853 {} lift:inst2|p2~854 {} lift:inst2|p2~855 {} lift:inst2|dr[2]~593 {} lift:inst2|dr[2]~572 {} lift:inst2|dr[2] {} lift:inst2|p3~1 {} lift:inst2|Mux2~270 {} lift:inst2|Mux2~271 {} lift:inst2|Mux2~281 {} lift:inst2|Mux2~276 {} lift:inst2|ladd[0]~87 {} lift:inst2|ladd[0] {} } { 0.000ns 0.000ns 2.900ns 8.100ns 4.200ns 0.400ns 0.400ns 3.900ns 0.000ns 0.400ns 0.400ns 2.100ns 0.400ns 0.400ns 0.000ns 2.300ns 2.000ns } { 0.000ns 2.000ns 0.900ns 0.900ns 1.700ns 1.700ns 1.700ns 1.300ns 1.400ns 1.700ns 1.600ns 1.700ns 1.700ns 1.200ns 1.400ns 1.700ns 1.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.900 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.900 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[2] {} } { 0.000ns 0.000ns 2.900ns 8.100ns } { 0.000ns 2.000ns 0.900ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "52.200 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[0] lift:inst2|p2~853 lift:inst2|p2~854 lift:inst2|p2~855 lift:inst2|dr[2]~593 lift:inst2|dr[2]~572 lift:inst2|dr[2] lift:inst2|p3~1 lift:inst2|Mux2~270 lift:inst2|Mux2~271 lift:inst2|Mux2~281 lift:inst2|Mux2~276 lift:inst2|ladd[0]~87 lift:inst2|ladd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "52.200 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[0] {} lift:inst2|p2~853 {} lift:inst2|p2~854 {} lift:inst2|p2~855 {} lift:inst2|dr[2]~593 {} lift:inst2|dr[2]~572 {} lift:inst2|dr[2] {} lift:inst2|p3~1 {} lift:inst2|Mux2~270 {} lift:inst2|Mux2~271 {} lift:inst2|Mux2~281 {} lift:inst2|Mux2~276 {} lift:inst2|ladd[0]~87 {} lift:inst2|ladd[0] {} } { 0.000ns 0.000ns 2.900ns 8.100ns 4.200ns 0.400ns 0.400ns 3.900ns 0.000ns 0.400ns 0.400ns 2.100ns 0.400ns 0.400ns 0.000ns 2.300ns 2.000ns } { 0.000ns 2.000ns 0.900ns 0.900ns 1.700ns 1.700ns 1.700ns 1.300ns 1.400ns 1.700ns 1.600ns 1.700ns 1.700ns 1.200ns 1.400ns 1.700ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.900 ns + " "Info: + Micro setup delay of destination is 1.900 ns" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.600 ns" { lift:inst2|ladd[0] lift:inst2|liftor~496 lift:inst2|liftor~509 lift:inst2|liftor~500 lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.600 ns" { lift:inst2|ladd[0] {} lift:inst2|liftor~496 {} lift:inst2|liftor~509 {} lift:inst2|liftor~500 {} lift:inst2|liftor[2] {} } { 0.000ns 0.400ns 0.400ns 0.000ns 0.400ns } { 0.000ns 1.600ns 1.200ns 1.400ns 1.200ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.900 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.900 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[2] {} } { 0.000ns 0.000ns 2.900ns 8.100ns } { 0.000ns 2.000ns 0.900ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "52.200 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[0] lift:inst2|p2~853 lift:inst2|p2~854 lift:inst2|p2~855 lift:inst2|dr[2]~593 lift:inst2|dr[2]~572 lift:inst2|dr[2] lift:inst2|p3~1 lift:inst2|Mux2~270 lift:inst2|Mux2~271 lift:inst2|Mux2~281 lift:inst2|Mux2~276 lift:inst2|ladd[0]~87 lift:inst2|ladd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "52.200 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[0] {} lift:inst2|p2~853 {} lift:inst2|p2~854 {} lift:inst2|p2~855 {} lift:inst2|dr[2]~593 {} lift:inst2|dr[2]~572 {} lift:inst2|dr[2] {} lift:inst2|p3~1 {} lift:inst2|Mux2~270 {} lift:inst2|Mux2~271 {} lift:inst2|Mux2~281 {} lift:inst2|Mux2~276 {} lift:inst2|ladd[0]~87 {} lift:inst2|ladd[0] {} } { 0.000ns 0.000ns 2.900ns 8.100ns 4.200ns 0.400ns 0.400ns 3.900ns 0.000ns 0.400ns 0.400ns 2.100ns 0.400ns 0.400ns 0.000ns 2.300ns 2.000ns } { 0.000ns 2.000ns 0.900ns 0.900ns 1.700ns 1.700ns 1.700ns 1.300ns 1.400ns 1.700ns 1.600ns 1.700ns 1.700ns 1.200ns 1.400ns 1.700ns 1.700ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "upin register lift:inst2\|ladd\[0\] register lift:inst2\|ladd\[0\] 41.32 MHz 24.2 ns Internal " "Info: Clock \"upin\" has Internal fmax of 41.32 MHz between source register \"lift:inst2\|ladd\[0\]\" and destination register \"lift:inst2\|ladd\[0\]\" (period= 24.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.700 ns + Longest register register " "Info: + Longest register to register delay is 11.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lift:inst2\|ladd\[0\] 1 REG LC1_H47 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_H47; Fanout = 6; REG Node = 'lift:inst2\|ladd\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lift:inst2|ladd[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 3.900 ns lift:inst2\|Mux1~757 2 COMB LC8_H48 1 " "Info: 2: + IC(2.200 ns) + CELL(1.700 ns) = 3.900 ns; Loc. = LC8_H48; Fanout = 1; COMB Node = 'lift:inst2\|Mux1~757'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { lift:inst2|ladd[0] lift:inst2|M