ff.tan.qmsg

QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 64 -32 136 80 "clkin" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "upin " "Info: Assuming node \"upin\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 80 -32 136 96 "upin" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "st_ch " "Info: Assuming node \"st_ch\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 112 -32 136 128 "st_ch" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "downin " "Info: Assuming node \"downin\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 96 -32 136 112 "downin" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "70 " "Warning: Found 70 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[5\] " "Info: Detected ripple clock \"lift:inst2\|ur\[5\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[5\] " "Info: Detected ripple clock \"lift:inst2\|dr\[5\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[6\] " "Info: Detected ripple clock \"lift:inst2\|ur\[6\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[6\] " "Info: Detected ripple clock \"lift:inst2\|dr\[6\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[4\] " "Info: Detected ripple clock \"lift:inst2\|ur\[4\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[4\] " "Info: Detected ripple clock \"lift:inst2\|dr\[4\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[1\] " "Info: Detected ripple clock \"lift:inst2\|ur\[1\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[1\] " "Info: Detected ripple clock \"lift:inst2\|dr\[1\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[2\] " "Info: Detected ripple clock \"lift:inst2\|dr\[2\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[2\] " "Info: Detected ripple clock \"lift:inst2\|ur\[2\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[3\] " "Info: Detected ripple clock \"lift:inst2\|ur\[3\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[3\] " "Info: Detected ripple clock \"lift:inst2\|dr\[3\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ur\[4\]~523 " "Info: Detected gated clock \"lift:inst2\|ur\[4\]~523\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[4\]~523" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[4\]~599 " "Info: Detected gated clock \"lift:inst2\|dr\[4\]~599\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[4\]~599" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ur\[1\]~520 " "Info: Detected gated clock \"lift:inst2\|ur\[1\]~520\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[1\]~520" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[1\]~596 " "Info: Detected gated clock \"lift:inst2\|dr\[1\]~596\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[1\]~596" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[2\]~593 " "Info: Detected gated clock \"lift:inst2\|dr\[2\]~593\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[2\]~593" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ur\[2\]~517 " "Info: Detected gated clock \"lift:inst2\|ur\[2\]~517\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[2\]~517" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ladd\[0\]~87 " "Info: Detected gated clock \"lift:inst2\|ladd\[0\]~87\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ladd\[0\]~87" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~274 " "Info: Detected gated clock \"lift:inst2\|Mux2~274\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~274" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~273 " "Info: Detected gated clock \"lift:inst2\|Mux2~273\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~273" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~281 " "Info: Detected gated clock \"lift:inst2\|Mux2~281\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~281" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~271 " "Info: Detected gated clock \"lift:inst2\|Mux2~271\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~271" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~270 " "Info: Detected gated clock \"lift:inst2\|Mux2~270\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~270" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ur\[5\]~485 " "Info: Detected gated clock \"lift:inst2\|ur\[5\]~485\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[5\]~485" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[5\]~556 " "Info: Detected gated clock \"lift:inst2\|dr\[5\]~556\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[5\]~556" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[5\]~555 " "Info: Detected gated clock \"lift:inst2\|dr\[5\]~555\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[5\]~555" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ur\[6\]~484 " "Info: Detected gated clock \"lift:inst2\|ur\[6\]~484\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[6\]~484" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[6\]~554 " "Info: Detected gated clock \"lift:inst2\|dr\[6\]~554\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[6\]~554" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[5\]~553 " "Info: Detected gated clock \"lift:inst2\|dr\[5\]~553\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[5\]~553" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Equal0~14 " "Info: Detected gated clock \"lift:inst2\|Equal0~14\" as buffer" {  } { { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Equal0~14" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ur\[4\]~503 " "Info: Detected gated clock \"lift:inst2\|ur\[4\]~503\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[4\]~503" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[4\]~574 " "Info: Detected gated clock \"lift:inst2\|dr\[4\]~574\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[4\]~574" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ur\[1\]~502 " "Info: Detected gated clock \"lift:inst2\|ur\[1\]~502\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[1\]~502" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[1\]~573 " "Info: Detected gated clock \"lift:inst2\|dr\[1\]~573\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[1\]~573" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[2\]~572 " "Info: Detected gated clock \"lift:inst2\|dr\[2\]~572\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[2\]~572" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ur\[2\]~501 " "Info: Detected gated clock \"lift:inst2\|ur\[2\]~501\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[2\]~501" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ur\[3\]~480 " "Info: Detected gated clock \"lift:inst2\|ur\[3\]~480\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[3\]~480" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p2~860 " "Info: Detected gated clock \"lift:inst2\|p2~860\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p2~860" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p2~859 " "Info: Detected gated clock \"lift:inst2\|p2~859\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p2~859" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p2~858 " "Info: Detected gated clock \"lift:inst2\|p2~858\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p2~858" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p2~857 " "Info: Detected gated clock \"lift:inst2\|p2~857\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p2~857" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p2~856 " "Info: Detected gated clock \"lift:inst2\|p2~856\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p2~856" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[3\]~548 " "Info: Detected gated clock \"lift:inst2\|dr\[3\]~548\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[3\]~548" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[1\]~547 " "Info: Detected gated clock \"lift:inst2\|dr\[1\]~547\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[1\]~547" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|dr\[3\]~546 " "Info: Detected gated clock \"lift:inst2\|dr\[3\]~546\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[3\]~546" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p2~855 " "Info: Detected gated clock \"lift:inst2\|p2~855\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p2~855" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p2~854 " "Info: Detected gated clock \"lift:inst2\|p2~854\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p2~854" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p2~853 " "Info: Detected gated clock \"lift:inst2\|p2~853\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p2~853" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p2~852 " "Info: Detected gated clock \"lift:inst2\|p2~852\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p2~852" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p2~851 " "Info: Detected gated clock \"lift:inst2\|p2~851\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p2~851" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p2~850 " "Info: Detected gated clock \"lift:inst2\|p2~850\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p2~850" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ladd\[1\]~84 " "Info: Detected gated clock \"lift:inst2\|ladd\[1\]~84\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ladd\[1\]~84" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Equal2~35 " "Info: Detected gated clock \"lift:inst2\|Equal2~35\" as buffer" {  } { { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Equal2~35" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p3~7 " "Info: Detected gated clock \"lift:inst2\|p3~7\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p3~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p3~0 " "Info: Detected gated clock \"lift:inst2\|p3~0\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p3~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p3~1 " "Info: Detected gated clock \"lift:inst2\|p3~1\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p3~1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p3~4 " "Info: Detected gated clock \"lift:inst2\|p3~4\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p3~4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|wai_t\[1\] " "Info: Detected ripple clock \"lift:inst2\|wai_t\[1\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|wai_t\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|wai_t\[2\] " "Info: Detected ripple clock \"lift:inst2\|wai_t\[2\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|wai_t\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dir\[1\] " "Info: Detected ripple clock \"lift:inst2\|dir\[1\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 43 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dir\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dir\[2\] " "Info: Detected ripple clock \"lift:inst2\|dir\[2\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 43 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dir\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "seg7dec:inst4\|segout\[5\]~305 " "Info: Detected gated clock \"seg7dec:inst4\|segout\[5\]~305\" as buffer" {  } { { "seg7dec.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/seg7dec.vhd" 6 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "seg7dec:inst4\|segout\[5\]~305" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|liftor\[1\] " "Info: Detected ripple clock \"lift:inst2\|liftor\[1\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|liftor\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|wai_t\[0\] " "Info: Detected ripple clock \"lift:inst2\|wai_t\[0\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|wai_t\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ladd\[1\]~85 " "Info: Detected gated clock \"lift:inst2\|ladd\[1\]~85\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ladd\[1\]~85" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~276 " "Info: Detected gated clock \"lift:inst2\|Mux2~276\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~276" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|liftor\[2\] " "Info: Detected ripple clock \"lift:inst2\|liftor\[2\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|liftor\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dir\[0\] " "Info: Detected ripple clock \"lift:inst2\|dir\[0\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 43 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dir\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|liftor\[0\] " "Info: Detected ripple clock \"lift:inst2\|liftor\[0\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|liftor\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}