prev_cmp_ff.tan.qmsg

QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clkin 5 " "Warning: Circuit may not operate. Detected 5 non-operational path(s) clocked by clock \"clkin\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lift:inst2\|liftor\[2\] lift:inst2\|ladd\[0\] clkin 9.6 ns " "Info: Found hold time violation between source  pin or register \"lift:inst2\|liftor\[2\]\" and destination pin or register \"lift:inst2\|ladd\[0\]\" for clock \"clkin\" (Hold time is 9.6 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "18.200 ns + Largest " "Info: + Largest clock skew is 18.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 34.200 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 34.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkin 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 64 -32 136 80 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.900 ns) 5.800 ns lift:inst2\|dir\[0\] 2 REG LC1_I31 32 " "Info: 2: + IC(2.900 ns) + CELL(0.900 ns) = 5.800 ns; Loc. = LC1_I31; Fanout = 32; REG Node = 'lift:inst2\|dir\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { clkin lift:inst2|dir[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(10.200 ns) + CELL(0.900 ns) 16.900 ns lift:inst2\|liftor\[0\] 3 REG LC2_E12 22 " "Info: 3: + IC(10.200 ns) + CELL(0.900 ns) = 16.900 ns; Loc. = LC2_E12; Fanout = 22; REG Node = 'lift:inst2\|liftor\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.100 ns" { lift:inst2|dir[0] lift:inst2|liftor[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(1.700 ns) 21.600 ns lift:inst2\|Mux2~270 4 COMB LC7_E15 1 " "Info: 4: + IC(3.000 ns) + CELL(1.700 ns) = 21.600 ns; Loc. = LC7_E15; Fanout = 1; COMB Node = 'lift:inst2\|Mux2~270'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { lift:inst2|liftor[0] lift:inst2|Mux2~270 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.700 ns) 23.700 ns lift:inst2\|Mux2~271 5 COMB LC5_E15 1 " "Info: 5: + IC(0.400 ns) + CELL(1.700 ns) = 23.700 ns; Loc. = LC5_E15; Fanout = 1; COMB Node = 'lift:inst2\|Mux2~271'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lift:inst2|Mux2~270 lift:inst2|Mux2~271 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.200 ns) 26.900 ns lift:inst2\|Mux2~281 6 COMB LC4_E12 1 " "Info: 6: + IC(2.000 ns) + CELL(1.200 ns) = 26.900 ns; Loc. = LC4_E12; Fanout = 1; COMB Node = 'lift:inst2\|Mux2~281'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { lift:inst2|Mux2~271 lift:inst2|Mux2~281 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 28.300 ns lift:inst2\|Mux2~276 7 COMB LC5_E12 2 " "Info: 7: + IC(0.000 ns) + CELL(1.400 ns) = 28.300 ns; Loc. = LC5_E12; Fanout = 2; COMB Node = 'lift:inst2\|Mux2~276'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { lift:inst2|Mux2~281 lift:inst2|Mux2~276 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.700 ns) 30.400 ns lift:inst2\|ladd\[0\]~88 8 COMB LC6_E12 1 " "Info: 8: + IC(0.400 ns) + CELL(1.700 ns) = 30.400 ns; Loc. = LC6_E12; Fanout = 1; COMB Node = 'lift:inst2\|ladd\[0\]~88'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lift:inst2|Mux2~276 lift:inst2|ladd[0]~88 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.700 ns) 34.200 ns lift:inst2\|ladd\[0\] 9 REG LC6_E13 6 " "Info: 9: + IC(2.100 ns) + CELL(1.700 ns) = 34.200 ns; Loc. = LC6_E13; Fanout = 6; REG Node = 'lift:inst2\|ladd\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { lift:inst2|ladd[0]~88 lift:inst2|ladd[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.200 ns ( 38.60 % ) " "Info: Total cell delay = 13.200 ns ( 38.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "21.000 ns ( 61.40 % ) " "Info: Total interconnect delay = 21.000 ns ( 61.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "34.200 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[0] lift:inst2|Mux2~270 lift:inst2|Mux2~271 lift:inst2|Mux2~281 lift:inst2|Mux2~276 lift:inst2|ladd[0]~88 lift:inst2|ladd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "34.200 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[0] {} lift:inst2|Mux2~270 {} lift:inst2|Mux2~271 {} lift:inst2|Mux2~281 {} lift:inst2|Mux2~276 {} lift:inst2|ladd[0]~88 {} lift:inst2|ladd[0] {} } { 0.000ns 0.000ns 2.900ns 10.200ns 3.000ns 0.400ns 2.000ns 0.000ns 0.400ns 2.100ns } { 0.000ns 2.000ns 0.900ns 0.900ns 1.700ns 1.700ns 1.200ns 1.400ns 1.700ns 1.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 16.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to source register is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkin 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 64 -32 136 80 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.900 ns) 5.800 ns lift:inst2\|dir\[0\] 2 REG LC1_I31 32 " "Info: 2: + IC(2.900 ns) + CELL(0.900 ns) = 5.800 ns; Loc. = LC1_I31; Fanout = 32; REG Node = 'lift:inst2\|dir\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { clkin lift:inst2|dir[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(10.200 ns) + CELL(0.000 ns) 16.000 ns lift:inst2\|liftor\[2\] 3 REG LC1_E13 20 " "Info: 3: + IC(10.200 ns) + CELL(0.000 ns) = 16.000 ns; Loc. = LC1_E13; Fanout = 20; REG Node = 'lift:inst2\|liftor\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 18.13 % ) " "Info: Total cell delay = 2.900 ns ( 18.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.100 ns ( 81.88 % ) " "Info: Total interconnect delay = 13.100 ns ( 81.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.000 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[2] {} } { 0.000ns 0.000ns 2.900ns 10.200ns } { 0.000ns 2.000ns 0.900ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "34.200 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[0] lift:inst2|Mux2~270 lift:inst2|Mux2~271 lift:inst2|Mux2~281 lift:inst2|Mux2~276 lift:inst2|ladd[0]~88 lift:inst2|ladd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "34.200 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[0] {} lift:inst2|Mux2~270 {} lift:inst2|Mux2~271 {} lift:inst2|Mux2~281 {} lift:inst2|Mux2~276 {} lift:inst2|ladd[0]~88 {} lift:inst2|ladd[0] {} } { 0.000ns 0.000ns 2.900ns 10.200ns 3.000ns 0.400ns 2.000ns 0.000ns 0.400ns 2.100ns } { 0.000ns 2.000ns 0.900ns 0.900ns 1.700ns 1.700ns 1.200ns 1.400ns 1.700ns 1.700ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.000 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[2] {} } { 0.000ns 0.000ns 2.900ns 10.200ns } { 0.000ns 2.000ns 0.900ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns - " "Info: - Micro clock to output delay of source is 0.900 ns" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.700 ns - Shortest register register " "Info: - Shortest register to register delay is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lift:inst2\|liftor\[2\] 1 REG LC1_E13 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E13; Fanout = 20; REG Node = 'lift:inst2\|liftor\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lift:inst2|liftor[2] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.700 ns) 4.000 ns lift:inst2\|Mux1~762 2 COMB LC2_E15 1 " "Info: 2: + IC(2.300 ns) + CELL(1.700 ns) = 4.000 ns; Loc. = LC2_E15; Fanout = 1; COMB Node = 'lift:inst2\|Mux1~762'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { lift:inst2|liftor[2] lift:inst2|Mux1~762 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.700 ns) 7.700 ns lift:inst2\|ladd\[0\] 3 REG LC6_E13 6 " "Info: 3: + IC(2.000 ns) + CELL(1.700 ns) = 7.700 ns; Loc. = LC6_E13; Fanout = 6; REG Node = 'lift:inst2\|ladd\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { lift:inst2|Mux1~762 lift:inst2|ladd[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 44.16 % ) " "Info: Total cell delay = 3.400 ns ( 44.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 55.84 % ) " "Info: Total interconnect delay = 4.300 ns ( 55.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { lift:inst2|liftor[2] lift:inst2|Mux1~762 lift:inst2|ladd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.700 ns" { lift:inst2|liftor[2] {} lift:inst2|Mux1~762 {} lift:inst2|ladd[0] {} } { 0.000ns 2.300ns 2.000ns } { 0.000ns 1.700ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "34.200 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[0] lift:inst2|Mux2~270 lift:inst2|Mux2~271 lift:inst2|Mux2~281 lift:inst2|Mux2~276 lift:inst2|ladd[0]~88 lift:inst2|ladd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "34.200 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[0] {} lift:inst2|Mux2~270 {} lift:inst2|Mux2~271 {} lift:inst2|Mux2~281 {} lift:inst2|Mux2~276 {} lift:inst2|ladd[0]~88 {} lift:inst2|ladd[0] {} } { 0.000ns 0.000ns 2.900ns 10.200ns 3.000ns 0.400ns 2.000ns 0.000ns 0.400ns 2.100ns } { 0.000ns 2.000ns 0.900ns 0.900ns 1.700ns 1.700ns 1.200ns 1.400ns 1.700ns 1.700ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.000 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[2] {} } { 0.000ns 0.000ns 2.900ns 10.200ns } { 0.000ns 2.000ns 0.900ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { lift:inst2|liftor[2] lift:inst2|Mux1~762 lift:inst2|ladd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.700 ns" { lift:inst2|liftor[2] {} lift:inst2|Mux1~762 {} lift:inst2|ladd[0] {} } { 0.000ns 2.300ns 2.000ns } { 0.000ns 1.700ns 1.700ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "lift:inst2\|wai_t\[1\] close clkin 3.700 ns register " "Info: tsu for register \"lift:inst2\|wai_t\[1\]\" (data pin = \"close\", clock pin = \"clkin\") is 3.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.800 ns + Longest pin register " "Info: + Longest pin to register delay is 17.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.200 ns) 7.200 ns close 1 PIN PIN_116 2 " "Info: 1: + IC(0.000 ns) + CELL(7.200 ns) = 7.200 ns; Loc. = PIN_116; Fanout = 2; PIN Node = 'close'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { close } "NODE_NAME" } } { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 128 -32 136 144 "close" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.300 ns) + CELL(1.700 ns) 14.200 ns lift:inst2\|p4~0 2 COMB LC5_E11 3 " "Info: 2: + IC(5.300 ns) + CELL(1.700 ns) = 14.200 ns; Loc. = LC5_E11; Fanout = 3; COMB Node = 'lift:inst2\|p4~0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { close lift:inst2|p4~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.600 ns) 16.200 ns lift:inst2\|wai_t~121 3 COMB LC8_E11 1 " "Info: 3: + IC(0.400 ns) + CELL(1.600 ns) = 16.200 ns; Loc. = LC8_E11; Fanout = 1; COMB Node = 'lift:inst2\|wai_t~121'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { lift:inst2|p4~0 lift:inst2|wai_t~121 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.200 ns) 17.800 ns lift:inst2\|wai_t\[1\] 4 REG LC6_E11 6 " "Info: 4: + IC(0.400 ns) + CELL(1.200 ns) = 17.800 ns; Loc. = LC6_E11; Fanout = 6; REG Node = 'lift:inst2\|wai_t\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { lift:inst2|wai_t~121 lift:inst2|wai_t[1] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.700 ns ( 65.73 % ) " "Info: Total cell delay = 11.700 ns ( 65.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns ( 34.27 % ) " "Info: Total interconnect delay = 6.100 ns ( 34.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.800 ns" { close lift:inst2|p4~0 lift:inst2|wai_t~121 lift:inst2|wai_t[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "17.800 ns" { close {} close~out {} lift:inst2|p4~0 {} lift:inst2|wai_t~121 {} lift:inst2|wai_t[1] {} } { 0.000ns 0.000ns 5.300ns 0.400ns 0.400ns } { 0.000ns 7.200ns 1.700ns 1.600ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.900 ns + " "Info: + Micro setup delay of destination is 1.900 ns" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 16.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkin 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 64 -32 136 80 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.900 ns) 5.800 ns lift:inst2\|dir\[0\] 2 REG LC1_I31 32 " "Info: 2: + IC(2.900 ns) + CELL(