prev_cmp_ff.tan.qmsg

QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 64 -32 136 80 "clkin" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "34 " "Warning: Found 34 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[5\] " "Info: Detected ripple clock \"lift:inst2\|ur\[5\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[5\] " "Info: Detected ripple clock \"lift:inst2\|dr\[5\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[6\] " "Info: Detected ripple clock \"lift:inst2\|ur\[6\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[6\] " "Info: Detected ripple clock \"lift:inst2\|dr\[6\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[4\] " "Info: Detected ripple clock \"lift:inst2\|dr\[4\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[4\] " "Info: Detected ripple clock \"lift:inst2\|ur\[4\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[1\] " "Info: Detected ripple clock \"lift:inst2\|ur\[1\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[1\] " "Info: Detected ripple clock \"lift:inst2\|dr\[1\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[2\] " "Info: Detected ripple clock \"lift:inst2\|ur\[2\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[2\] " "Info: Detected ripple clock \"lift:inst2\|dr\[2\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|ur\[3\] " "Info: Detected ripple clock \"lift:inst2\|ur\[3\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ur\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dr\[3\] " "Info: Detected ripple clock \"lift:inst2\|dr\[3\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dr\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ladd\[0\]~88 " "Info: Detected gated clock \"lift:inst2\|ladd\[0\]~88\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ladd\[0\]~88" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~274 " "Info: Detected gated clock \"lift:inst2\|Mux2~274\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~274" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~273 " "Info: Detected gated clock \"lift:inst2\|Mux2~273\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~273" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~281 " "Info: Detected gated clock \"lift:inst2\|Mux2~281\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~281" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~271 " "Info: Detected gated clock \"lift:inst2\|Mux2~271\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~271" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~270 " "Info: Detected gated clock \"lift:inst2\|Mux2~270\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~270" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ladd\[1\]~85 " "Info: Detected gated clock \"lift:inst2\|ladd\[1\]~85\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ladd\[1\]~85" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Equal2~35 " "Info: Detected gated clock \"lift:inst2\|Equal2~35\" as buffer" {  } { { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Equal2~35" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p3~7 " "Info: Detected gated clock \"lift:inst2\|p3~7\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p3~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p3~0 " "Info: Detected gated clock \"lift:inst2\|p3~0\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p3~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p3~1 " "Info: Detected gated clock \"lift:inst2\|p3~1\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p3~1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|p3~4 " "Info: Detected gated clock \"lift:inst2\|p3~4\" as buffer" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|p3~4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|wai_t\[1\] " "Info: Detected ripple clock \"lift:inst2\|wai_t\[1\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|wai_t\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|wai_t\[2\] " "Info: Detected ripple clock \"lift:inst2\|wai_t\[2\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|wai_t\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "seg7dec:inst4\|segout\[5\]~306 " "Info: Detected gated clock \"seg7dec:inst4\|segout\[5\]~306\" as buffer" {  } { { "seg7dec.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/seg7dec.vhd" 6 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "seg7dec:inst4\|segout\[5\]~306" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|liftor\[1\] " "Info: Detected ripple clock \"lift:inst2\|liftor\[1\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|liftor\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|wai_t\[0\] " "Info: Detected ripple clock \"lift:inst2\|wai_t\[0\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|wai_t\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|ladd\[1\]~86 " "Info: Detected gated clock \"lift:inst2\|ladd\[1\]~86\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|ladd\[1\]~86" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lift:inst2\|Mux2~276 " "Info: Detected gated clock \"lift:inst2\|Mux2~276\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|Mux2~276" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|liftor\[2\] " "Info: Detected ripple clock \"lift:inst2\|liftor\[2\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|liftor\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|dir\[0\] " "Info: Detected ripple clock \"lift:inst2\|dir\[0\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 43 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|dir\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lift:inst2\|liftor\[0\] " "Info: Detected ripple clock \"lift:inst2\|liftor\[0\]\" as buffer" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lift:inst2\|liftor\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register lift:inst2\|ladd\[0\] register lift:inst2\|liftor\[2\] 18.73 MHz 53.4 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 18.73 MHz between source register \"lift:inst2\|ladd\[0\]\" and destination register \"lift:inst2\|liftor\[2\]\" (period= 53.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.600 ns + Longest register register " "Info: + Longest register to register delay is 6.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lift:inst2\|ladd\[0\] 1 REG LC6_E13 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_E13; Fanout = 6; REG Node = 'lift:inst2\|ladd\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lift:inst2|ladd[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.600 ns) 2.000 ns lift:inst2\|liftor~496 2 COMB LC5_E13 1 " "Info: 2: + IC(0.400 ns) + CELL(1.600 ns) = 2.000 ns; Loc. = LC5_E13; Fanout = 1; COMB Node = 'lift:inst2\|liftor~496'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { lift:inst2|ladd[0] lift:inst2|liftor~496 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.200 ns) 3.600 ns lift:inst2\|liftor~509 3 COMB LC3_E13 1 " "Info: 3: + IC(0.400 ns) + CELL(1.200 ns) = 3.600 ns; Loc. = LC3_E13; Fanout = 1; COMB Node = 'lift:inst2\|liftor~509'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { lift:inst2|liftor~496 lift:inst2|liftor~509 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 5.000 ns lift:inst2\|liftor~500 4 COMB LC4_E13 1 " "Info: 4: + IC(0.000 ns) + CELL(1.400 ns) = 5.000 ns; Loc. = LC4_E13; Fanout = 1; COMB Node = 'lift:inst2\|liftor~500'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { lift:inst2|liftor~509 lift:inst2|liftor~500 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.200 ns) 6.600 ns lift:inst2\|liftor\[2\] 5 REG LC1_E13 20 " "Info: 5: + IC(0.400 ns) + CELL(1.200 ns) = 6.600 ns; Loc. = LC1_E13; Fanout = 20; REG Node = 'lift:inst2\|liftor\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { lift:inst2|liftor~500 lift:inst2|liftor[2] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.400 ns ( 81.82 % ) " "Info: Total cell delay = 5.400 ns ( 81.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 18.18 % ) " "Info: Total interconnect delay = 1.200 ns ( 18.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.600 ns" { lift:inst2|ladd[0] lift:inst2|liftor~496 lift:inst2|liftor~509 lift:inst2|liftor~500 lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.600 ns" { lift:inst2|ladd[0] {} lift:inst2|liftor~496 {} lift:inst2|liftor~509 {} lift:inst2|liftor~500 {} lift:inst2|liftor[2] {} } { 0.000ns 0.400ns 0.400ns 0.000ns 0.400ns } { 0.000ns 1.600ns 1.200ns 1.400ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-18.200 ns - Smallest " "Info: - Smallest clock skew is -18.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 16.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkin 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 64 -32 136 80 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.900 ns) 5.800 ns lift:inst2\|dir\[0\] 2 REG LC1_I31 32 " "Info: 2: + IC(2.900 ns) + CELL(0.900 ns) = 5.800 ns; Loc. = LC1_I31; Fanout = 32; REG Node = 'lift:inst2\|dir\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { clkin lift:inst2|dir[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(10.200 ns) + CELL(0.000 ns) 16.000 ns lift:inst2\|liftor\[2\] 3 REG LC1_E13 20 " "Info: 3: + IC(10.200 ns) + CELL(0.000 ns) = 16.000 ns; Loc. = LC1_E13; Fanout = 20; REG Node = 'lift:inst2\|liftor\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 18.13 % ) " "Info: Total cell delay = 2.900 ns ( 18.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.100 ns ( 81.88 % ) " "Info: Total interconnect delay = 13.100 ns ( 81.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.000 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[2] {} } { 0.000ns 0.000ns 2.900ns 10.200ns } { 0.000ns 2.000ns 0.900ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 34.200 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 34.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkin 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 64 -32 136 80 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.900 ns) 5.800 ns lift:inst2\|dir\[0\] 2 REG LC1_I31 32 " "Info: 2: + IC(2.900 ns) + CELL(0.900 ns) = 5.800 ns; Loc. = LC1_I31; Fanout = 32; REG Node = 'lift:inst2\|dir\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { clkin lift:inst2|dir[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(10.200 ns) + CELL(0.900 ns) 16.900 ns lift:inst2\|liftor\[0\] 3 REG LC2_E12 22 " "Info: 3: + IC(10.200 ns) + CELL(0.900 ns) = 16.900 ns; Loc. = LC2_E12; Fanout = 22; REG Node = 'lift:inst2\|liftor\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.100 ns" { lift:inst2|dir[0] lift:inst2|liftor[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(1.700 ns) 21.600 ns lift:inst2\|Mux2~270 4 COMB LC7_E15 1 " "Info: 4: + IC(3.000 ns) + CELL(1.700 ns) = 21.600 ns; Loc. = LC7_E15; Fanout = 1; COMB Node = 'lift:inst2\|Mux2~270'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { lift:inst2|liftor[0] lift:inst2|Mux2~270 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.700 ns) 23.700 ns lift:inst2\|Mux2~271 5 COMB LC5_E15 1 " "Info: 5: + IC(0.400 ns) + CELL(1.700 ns) = 23.700 ns; Loc. = LC5_E15; Fanout = 1; COMB Node = 'lift:inst2\|Mux2~271'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lift:inst2|Mux2~270 lift:inst2|Mux2~271 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.200 ns) 26.900 ns lift:inst2\|Mux2~281 6 COMB LC4_E12 1 " "Info: 6: + IC(2.000 ns) + CELL(1.200 ns) = 26.900 ns; Loc. = LC4_E12; Fanout = 1; COMB Node = 'lift:inst2\|Mux2~281'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { lift:inst2|Mux2~271 lift:inst2|Mux2~281 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 28.300 ns lift:inst2\|Mux2~276 7 COMB LC5_E12 2 " "Info: 7: + IC(0.000 ns) + CELL(1.400 ns) = 28.300 ns; Loc. = LC5_E12; Fanout = 2; COMB Node = 'lift:inst2\|Mux2~276'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { lift:inst2|Mux2~281 lift:inst2|Mux2~276 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.700 ns) 30.400 ns lift:inst2\|ladd\[0\]~88 8 COMB LC6_E12 1 " "Info: 8: + IC(0.400 ns) + CELL(1.700 ns) = 30.400 ns; Loc. = LC6_E12; Fanout = 1; COMB Node = 'lift:inst2\|ladd\[0\]~88'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lift:inst2|Mux2~276 lift:inst2|ladd[0]~88 } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.700 ns) 34.200 ns lift:inst2\|ladd\[0\] 9 REG LC6_E13 6 " "Info: 9: + IC(2.100 ns) + CELL(1.700 ns) = 34.200 ns; Loc. = LC6_E13; Fanout = 6; REG Node = 'lift:inst2\|ladd\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { lift:inst2|ladd[0]~88 lift:inst2|ladd[0] } "NODE_NAME" } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.200 ns ( 38.60 % ) " "Info: Total cell delay = 13.200 ns ( 38.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "21.000 ns ( 61.40 % ) " "Info: Total interconnect delay = 21.000 ns ( 61.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "34.200 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[0] lift:inst2|Mux2~270 lift:inst2|Mux2~271 lift:inst2|Mux2~281 lift:inst2|Mux2~276 lift:inst2|ladd[0]~88 lift:inst2|ladd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "34.200 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[0] {} lift:inst2|Mux2~270 {} lift:inst2|Mux2~271 {} lift:inst2|Mux2~281 {} lift:inst2|Mux2~276 {} lift:inst2|ladd[0]~88 {} lift:inst2|ladd[0] {} } { 0.000ns 0.000ns 2.900ns 10.200ns 3.000ns 0.400ns 2.000ns 0.000ns 0.400ns 2.100ns } { 0.000ns 2.000ns 0.900ns 0.900ns 1.700ns 1.700ns 1.200ns 1.400ns 1.700ns 1.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.000 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[2] {} } { 0.000ns 0.000ns 2.900ns 10.200ns } { 0.000ns 2.000ns 0.900ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "34.200 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[0] lift:inst2|Mux2~270 lift:inst2|Mux2~271 lift:inst2|Mux2~281 lift:inst2|Mux2~276 lift:inst2|ladd[0]~88 lift:inst2|ladd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "34.200 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[0] {} lift:inst2|Mux2~270 {} lift:inst2|Mux2~271 {} lift:inst2|Mux2~281 {} lift:inst2|Mux2~276 {} lift:inst2|ladd[0]~88 {} lift:inst2|ladd[0] {} } { 0.000ns 0.000ns 2.900ns 10.200ns 3.000ns 0.400ns 2.000ns 0.000ns 0.400ns 2.100ns } { 0.000ns 2.000ns 0.900ns 0.900ns 1.700ns 1.700ns 1.200ns 1.400ns 1.700ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.900 ns + " "Info: + Micro setup delay of destination is 1.900 ns" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } } { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.600 ns" { lift:inst2|ladd[0] lift:inst2|liftor~496 lift:inst2|liftor~509 lift:inst2|liftor~500 lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.600 ns" { lift:inst2|ladd[0] {} lift:inst2|liftor~496 {} lift:inst2|liftor~509 {} lift:inst2|liftor~500 {} lift:inst2|liftor[2] {} } { 0.000ns 0.400ns 0.400ns 0.000ns 0.400ns } { 0.000ns 1.600ns 1.200ns 1.400ns 1.200ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.000 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[2] {} } { 0.000ns 0.000ns 2.900ns 10.200ns } { 0.000ns 2.000ns 0.900ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "34.200 ns" { clkin lift:inst2|dir[0] lift:inst2|liftor[0] lift:inst2|Mux2~270 lift:inst2|Mux2~271 lift:inst2|Mux2~281 lift:inst2|Mux2~276 lift:inst2|ladd[0]~88 lift:inst2|ladd[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "34.200 ns" { clkin {} clkin~out {} lift:inst2|dir[0] {} lift:inst2|liftor[0] {} lift:inst2|Mux2~270 {} lift:inst2|Mux2~271 {} lift:inst2|Mux2~281 {} lift:inst2|Mux2~276 {} lift:inst2|ladd[0]~88 {} lift:inst2|ladd[0] {} } { 0.000ns 0.000ns 2.900ns 10.200ns 3.000ns 0.400ns 2.000ns 0.000ns 0.400ns 2.100ns } { 0.000ns 2.000ns 0.900ns 0.900ns 1.700ns 1.700ns 1.200ns 1.400ns 1.700ns 1.700ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}