ssd2.vhd

在Xilinx7.1平台下编写

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-- Company: 
-- Engineer:
--
-- Create Date:    13:33:51 11/02/08
-- Design Name:    
-- Module Name:    SSD2 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SSD2 is
	port
	(
		a :in std_logic_vector(3 downto 0);
		y :out std_logic_vector(6 downto 0)
	);
end SSD2;

architecture Behavioral of SSD2 is

begin
	y(6)<=(a(2) and (not a(1)) and (not a(0))) or ((not a(3)) and (not a(2)) and (not a(1)) and a(0));
	y(5)<=(a(2) and (not a(1)) and a(0)) or (a(2) and a(1) and (not a(0)));
	y(4)<=(not a(2)) and a(1) and (not a(0));
	y(3)<=(a(2) and (not a(1)) and (not a(0))) or (a(2) and a(1) and a(0)) or ((not a(3)) and (not a(2)) and (not a(1)) and a(0));
	y(2)<=(a(2) and (not a(1))) or a(0);
	y(1)<=(a(1) and a(0)) or ((not a(2)) and a(1)) or ((not a(3)) and (not a(2)) and a(0));
	y(0)<=((not a(3)) and (not a(2)) and (not a(1))) or (a(2) and a(1) and a(0));

end Behavioral;