alu.vhd

在Xilinx7.1平台下编写的ALU代码

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-- Company: 
-- Engineer:
--
-- Create Date:    14:20:28 11/26/08
-- Design Name:    
-- Module Name:    ALU - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
	port(
		  X,Y:in std_logic_vector(4 downto 0);
		  R,S,CLK:in std_logic;
		  Control:in std_logic_vector(1 downto 0);
		  Z:out std_logic_vector(4 downto 0)
		  );
end ALU;

architecture Behavioral of ALU is
	signal X1,Y1,Z1,S1,S3,S4:std_logic_vector(4 downto 0);
	signal Ctrl:std_logic_vector(1 downto 0);	
begin

	process(R,S,CLK,X)	 --寄存器A
	begin
		if(R = '0') then X1<="00000";
		elsif(S = '1')	then X1<="11111";
		elsif(CLK'event and CLK='1')	then X1<=X;
		end if;
	end process;

	process(R,S,CLK,Y)	--寄存器B
	begin
		if(R = '0') then Y1<="00000";
		elsif(S = '1')	then Y1<="11111";
		elsif(CLK'event and CLK='1')	then Y1<=Y;
		end if;
	end process;

	process(R,S,CLK,Z1)  --寄存器D
	begin
		if(R = '0') then Z<="00000";
		elsif(S = '1')	then Z<="11111";
		elsif(CLK'event and CLK='1')	then Z<=Z1;
		end if;
	end process;

	process(R,S,CLK,Control)	 --寄存器C
	begin
		if(R = '0') then Ctrl<="00";
		elsif(S = '1')	then Ctrl<="11";
		elsif(CLK'event and CLK='1')	then Ctrl<=Control;
		end if;
	end process;

	process(S1,S3,S4,Ctrl) --选择器
	begin
		case Ctrl is
			when"00" => Z1<=S1;
			when"01" => Z1<=S1;
			when"10" => Z1<=S3;
			when"11" => Z1<=S4;
			when others => Z1<="00000";
		end case;
	end process;

	process(X1,Y1,Ctrl) --加法和减法
	variable c:std_logic_vector(5 downto 0):="000000";
--	variable temp:std_logic;
	begin		
		for i in 0 to 4 loop
		S1(i)<=X1(i) xor Y1(i) xor c(i);
		if(Ctrl="00") then c(i+1):=(X1(i) and Y1(i)) or (X1(i) and c(i)) or (Y1(i) and c(i));--加法
		elsif(Ctrl="01") then c(i+1):=(not X1(i) and Y1(i)) or (not X1(i) and c(i)) or (Y1(i) and c(i));--执行减法时，将X1(i)取反
		end if;	
		end loop;
	end process;

--	process(X1,Y1) --减法
--	variable c:std_logic_vector(5 downto 0):="000000";
--	begin
--		for i in 0 to 4 loop
--		S2(i)<=X1(i) xor Y1(i) xor c(i);
--		c(i+1):=((not X1(i)) and Y1(i)) or ((not X1(i)) and c(i)) or (Y1(i) and c(i));
--		end loop;
--	end process;

	process(X1,Y1) --AND
	begin
		for i in 0 to 4 loop
		S3(i)<=X1(i) and Y1(i);
		end loop;
	end process;

	process(X1,Y1) --XOR
	begin
		for i in 0 to 4 loop
		S4(i)<=X1(i) xor Y1(i);
		end loop;
	end process;


end Behavioral;