seven.vhd

来自「IO设备vhdl语言1234556778892341」· VHDL 代码 · 共 40 行

--Seven-input majority Voter
LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY seven IS
PORT(
      men :     IN std_logic_vector(6 downto 0);
      pass1 :    out std_logic;
      pass2 : OUT std_logic);
END seven;



--Behavioural style architecture 
ARCHITECTURE behav OF seven IS
signal passorn_s : std_logic;
BEGIN

PROCESS(men)
  VARIABLE flag :std_logic_vector(2 downto 0);
    BEGIN
      flag:="000";
-- loop 
for i in 0 to 6 loop
  if (men(i)='1')then
      
      flag:=flag+1;
   else 
      flag:=flag+0;
end if;
end loop;

passorn_s<= flag(2);   ---- 

pass1<=not passorn_s;  --- LED 低电平有效，即亮
pass2<=not passorn_s;  --- BUZZER 低电平有效，	响
END PROCESS;
END behav;