glm.vhd

IO设备vhdl语言1234556778892341

library IEEE;
use IEEE.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
use work.all;
entity glm is
          port (
                    DATA_IN : in std_logic_vector (3 downto 0);     -- input data
                    EN      :      in  std_logic;                   -- enable the gray trans &led scan
                    LEDOUT : out std_logic_vector (3 downto 0);   -- 为方便仿真观察
                    DATAOUT : out std_logic_vector (3 downto 0)
                   
          );
end entity;

architecture bin2gary_arch of glm is
signal DATA_OUT :std_logic_vector (3 downto 0);
begin
          
          DATA_OUT(0) <= (DATA_IN(0) xor DATA_IN(1)) and EN;    -- GRAY CODE TRANS.
          DATA_OUT(1) <= (DATA_IN(1) xor DATA_IN(2)) and EN;
          DATA_OUT(2) <= (DATA_IN(2) xor DATA_IN(3)) and EN;
          DATA_OUT(3) <= DATA_IN(3) and EN;
          LEDOUT<=DATA_OUT;     --方便显示输出,LED静态显示和数码管静态显示
          DATAOUT<=DATA_OUT;
end architecture;