📄 glm.tan.rpt
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Classic Timing Analyzer report for glm
Sun Oct 19 19:29:48 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------------+-----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------------+-----------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 16.846 ns ; DATA_IN[1] ; LEDOUT[1] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------------+-----------+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------------+------------+
; N/A ; None ; 16.846 ns ; DATA_IN[1] ; LEDOUT[1] ;
; N/A ; None ; 16.270 ns ; DATA_IN[3] ; LEDOUT[2] ;
; N/A ; None ; 16.206 ns ; DATA_IN[0] ; LEDOUT[0] ;
; N/A ; None ; 15.914 ns ; DATA_IN[2] ; LEDOUT[1] ;
; N/A ; None ; 15.911 ns ; DATA_IN[2] ; LEDOUT[2] ;
; N/A ; None ; 15.862 ns ; DATA_IN[1] ; LEDOUT[0] ;
; N/A ; None ; 15.486 ns ; DATA_IN[3] ; LEDOUT[3] ;
; N/A ; None ; 14.726 ns ; EN ; LEDOUT[1] ;
; N/A ; None ; 14.721 ns ; EN ; LEDOUT[2] ;
; N/A ; None ; 14.345 ns ; DATA_IN[0] ; DATAOUT[0] ;
; N/A ; None ; 14.330 ns ; EN ; LEDOUT[3] ;
; N/A ; None ; 14.001 ns ; DATA_IN[1] ; DATAOUT[0] ;
; N/A ; None ; 13.994 ns ; DATA_IN[1] ; DATAOUT[1] ;
; N/A ; None ; 13.737 ns ; EN ; LEDOUT[0] ;
; N/A ; None ; 13.468 ns ; DATA_IN[3] ; DATAOUT[2] ;
; N/A ; None ; 13.109 ns ; DATA_IN[2] ; DATAOUT[2] ;
; N/A ; None ; 13.062 ns ; DATA_IN[2] ; DATAOUT[1] ;
; N/A ; None ; 13.053 ns ; DATA_IN[3] ; DATAOUT[3] ;
; N/A ; None ; 11.919 ns ; EN ; DATAOUT[2] ;
; N/A ; None ; 11.897 ns ; EN ; DATAOUT[3] ;
; N/A ; None ; 11.876 ns ; EN ; DATAOUT[0] ;
; N/A ; None ; 11.874 ns ; EN ; DATAOUT[1] ;
+-------+-------------------+-----------------+------------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sun Oct 19 19:29:47 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off glm -c glm --timing_analysis_only
Info: Longest tpd from source pin "DATA_IN[1]" to destination pin "LEDOUT[1]" is 16.846 ns
Info: 1: + IC(0.000 ns) + CELL(0.954 ns) = 0.954 ns; Loc. = PIN_A21; Fanout = 2; PIN Node = 'DATA_IN[1]'
Info: 2: + IC(8.248 ns) + CELL(0.624 ns) = 9.826 ns; Loc. = LCCOMB_X50_Y4_N20; Fanout = 2; COMB Node = 'DATA_OUT~3'
Info: 3: + IC(3.784 ns) + CELL(3.236 ns) = 16.846 ns; Loc. = PIN_W12; Fanout = 0; PIN Node = 'LEDOUT[1]'
Info: Total cell delay = 4.814 ns ( 28.58 % )
Info: Total interconnect delay = 12.032 ns ( 71.42 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 153 megabytes of memory during processing
Info: Processing ended: Sun Oct 19 19:29:48 2008
Info: Elapsed time: 00:00:01
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